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Maturity fixes and AXI extensions for write-through cache system (ope…
…nhwgroup#188) * : Fix PITON_ARIANE define issues * Fix write-back / cache read collision issue in serpent dcache. * Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment). * Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane. * Fix assertion in icache. * Correct JTAG timing constraints. * Fix parameter type in fpga toplevel (fix openhwgroup#168). * Remove conflicting bootrom from fpga file list. * This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs). * Fix byte offset of IPIs in CLINT * Disable DCache flushes on fence for write-through cache (not needed in that case) * Fix blocking assignments in ff process. * Fix register access issue in debug mode, only affects A0 (fix openhwgroup#179). * Fix multiple driver issue in PLIC * Do not assume replicated data in serpent dcache when reading from an NC region. * Another byte offset fix in IPIs (CLINT) * Add AXI64 compliance switch to dcache_mem * Fix genesys 2 constraints * Map serpent atomic requests onto AXI atomic/exclusive transactions. * Cleanup of AXI memory plumbing, add separate AXI adapter module. * Remove unneeded interface signals, increase wbuffer #pending tx * Fix verilator compilation issues in AXI adapter. * Delete unnecessary constraint * Delete duplicate module instance * Update gitlab CI script * Small fixes to make riscv atomics work with serpent_axi_adapter. * Update travis and gitlab-ci scripts * Register b responses for better timing. * Remove fpu div submodule, update Makefile paths and src lists * Constant bits in haltsum reduction must be 1 (AND reduction). * Switch to DTM from riscv-dbg submodule * Further cleanup fixes in AXI/serpent atomics * Bump riscv-dbg version
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@@ -15,40 +15,45 @@ | |
| // Author: Michael Schaffner <[email protected]>, ETH Zurich | ||
| // Date: 15.08.2018 | ||
| // Description: File list for OpenPiton flow | ||
| // src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/control_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv | ||
| // src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv | ||
| // src/fpu/src/pkg/fpnew_pkg.vhd | ||
| // src/fpu/src/pkg/fpnew_fmts_pkg.vhd | ||
| // src/fpu/src/pkg/fpnew_comps_pkg.vhd | ||
| // src/fpu/src/pkg/fpnew_pkg_constants.vhd | ||
| // src/fpu/src/utils/fp_pipe.vhd | ||
| // src/fpu/src/utils/fp_rounding.vhd | ||
| // src/fpu/src/utils/fp_arbiter.vhd | ||
| // src/fpu/src/ops/fma_core.vhd | ||
| // src/fpu/src/ops/fp_fma.vhd | ||
| // src/fpu/src/ops/fp_divsqrt_multi.vhd | ||
| // src/fpu/src/ops/fp_noncomp.vhd | ||
| // src/fpu/src/ops/fp_f2fcasts_fmt.vhd | ||
| // src/fpu/src/ops/fp_f2icasts_fmt.vhd | ||
| // src/fpu/src/ops/fp_i2fcasts_fmt.vhd | ||
| // src/fpu/src/subunits/addmul_fmt_slice.vhd | ||
| // src/fpu/src/subunits/addmul_block.vhd | ||
| // src/fpu/src/subunits/divsqrt_multifmt_slice.vhd | ||
| // src/fpu/src/subunits/divsqrt_block.vhd | ||
| // src/fpu/src/subunits/noncomp_fmt_slice.vhd | ||
| // src/fpu/src/subunits/noncomp_block.vhd | ||
| // src/fpu/src/subunits/conv_fmt_slice.vhd | ||
| // src/fpu/src/subunits/conv_ifmt_slice.vhd | ||
| // src/fpu/src/subunits/conv_block.vhd | ||
| // src/fpu/src/fpnew.vhd | ||
| // src/fpu/src/fpnew_top.vhd | ||
| src/common_cells/include/common_cells/registers.svh | ||
| src/common_cells/src/fifo_v1.sv | ||
| src/common_cells/src/fifo_v2.sv | ||
| src/common_cells/src/fifo_v3.sv | ||
| src/common_cells/src/lfsr_8bit.sv | ||
| src/common_cells/src/lzc.sv | ||
| src/common_cells/src/rrarbiter.sv | ||
| src/common_cells/src/rstgen_bypass.sv | ||
| src/common_cells/src/sync_wedge.sv | ||
| src/common_cells/src/cdc_2phase.sv | ||
| src/common_cells/src/pipe_reg_simple.sv | ||
| src/common_cells/src/stream_arbiter_flushable.sv | ||
| src/common_cells/src/shift_reg.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv | ||
| src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv | ||
| src/fpu/src/fpnew_cast_multi.sv | ||
| src/fpu/src/fpnew_classifier.sv | ||
| src/fpu/src/fpnew_divsqrt_multi.sv | ||
| src/fpu/src/fpnew_f2fcast.sv | ||
| src/fpu/src/fpnew_f2icast.sv | ||
| src/fpu/src/fpnew_fma_multi.sv | ||
| src/fpu/src/fpnew_fma.sv | ||
| src/fpu/src/fpnew_i2fcast.sv | ||
| src/fpu/src/fpnew_noncomp.sv | ||
| src/fpu/src/fpnew_opgroup_block.sv | ||
| src/fpu/src/fpnew_opgroup_fmt_slice.sv | ||
| src/fpu/src/fpnew_opgroup_multifmt_slice.sv | ||
| src/fpu/src/fpnew_pipe_in.sv | ||
| src/fpu/src/fpnew_pipe_out.sv | ||
| src/fpu/src/fpnew_pkg.sv | ||
| src/fpu/src/fpnew_rounding.sv | ||
| src/fpu/src/fpnew_top.sv | ||
| src/axi/src/axi_pkg.sv | ||
| src/debug/dm_pkg.sv | ||
| include/riscv_pkg.sv | ||
|
|
@@ -64,16 +69,6 @@ src/util/axi_master_connect.sv | |
| src/util/axi_master_connect_rev.sv | ||
| src/util/axi_slave_connect.sv | ||
| src/util/axi_slave_connect_rev.sv | ||
| src/common_cells/src/fifo_v1.sv | ||
| src/common_cells/src/fifo_v2.sv | ||
| src/common_cells/src/fifo_v3.sv | ||
| src/common_cells/src/lfsr_8bit.sv | ||
| src/common_cells/src/lzc.sv | ||
| src/common_cells/src/rrarbiter.sv | ||
| src/common_cells/src/rstgen_bypass.sv | ||
| src/common_cells/src/sync_wedge.sv | ||
| src/common_cells/src/cdc_2phase.sv | ||
| src/common_cells/src/pipe_reg_simple.sv | ||
| src/fpga-support/rtl/SyncSpRamBeNx64.sv | ||
| src/axi_mem_if/src/axi2mem.sv | ||
| src/tech_cells_generic/src/cluster_clock_inverter.sv | ||
|
|
@@ -122,19 +117,19 @@ src/cache_subsystem/serpent_dcache.sv | |
| src/cache_subsystem/serpent_icache.sv | ||
| src/cache_subsystem/serpent_l15_adapter.sv | ||
| src/cache_subsystem/serpent_cache_subsystem.sv | ||
| src/debug/dm_csrs.sv | ||
| src/clint/clint.sv | ||
| src/clint/axi_lite_interface.sv | ||
| src/debug/dm_mem.sv | ||
| src/debug/dm_top.sv | ||
| src/debug/dmi_cdc.sv | ||
| src/debug/dmi_jtag.sv | ||
| src/debug/dm_sba.sv | ||
| src/debug/dmi_jtag_tap.sv | ||
| src/debug/debug_rom/debug_rom.sv | ||
| src/riscv-dbg/src/dm_csrs.sv | ||
| src/riscv-dbg/src/dm_mem.sv | ||
| src/riscv-dbg/src/dm_top.sv | ||
| src/riscv-dbg/src/dmi_cdc.sv | ||
| src/riscv-dbg/src/dmi_jtag.sv | ||
| src/riscv-dbg/src/dm_sba.sv | ||
| src/riscv-dbg/src/dmi_jtag_tap.sv | ||
| src/riscv-dbg/debug_rom/debug_rom.sv | ||
| openpiton/ariane_verilog_wrap.sv | ||
| openpiton/serpent_peripherals.sv | ||
| bootrom/bootrom.sv | ||
| openpiton/bootrom/bootrom.sv | ||
| src/plic/plic.sv | ||
| src/plic/plic_claim_complete_tracker.sv | ||
| src/plic/plic_comparator.sv | ||
|
|
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