Refactor serpent AXI adapter, bump dbg and atomics submodules, add se…

…parate bootrom for linux on OpenPiton (openhwgroup#190)

* Refactor serpent AXI adapter

* Disable FPU in OpenPiton by default

* Bump dbg and atomics submodules

* Fix cache testbenches (interface change)

* FPGA bootrom changes for OpenPiton SDHC

* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD

* Testing barrier-based synchronisation instead of CLINT-based

* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707

* Add MAX_HARTS switch to makefile

* Fix gitlab CI

* Revert standard FPGA bootrom

* Update Flist

* Make UART_FREQ a parameter

* Fix typo in tb.list and an error in define switch in ariane_pkg

* Copy over SD-driver in bootloader from @leon575777642

* Fix compilation issues of bootrom

* Change signal name in serpent periph portlist

* Correct generate statement in serpent dcache memory

.gitlab-ci.yml

@@ -113,7 +113,7 @@ amo-ver:
 fp-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-fp-tests-verilator 
+    - make -j${NUM_JOBS} run-fp-verilator 
   dependencies:
     - build
 
@@ -217,7 +217,7 @@ amo-ver:
 s-fp-ver:
   stage: serpent
   script:
-    - make -j${NUM_JOBS} run-fp-tests-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-fp-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
   dependencies:
     - build
 

Flist.ariane

@@ -15,7 +15,7 @@
 // Author: Michael Schaffner <[email protected]>, ETH Zurich
 // Date: 15.08.2018
 // Description: File list for OpenPiton flow
-src/common_cells/include/common_cells/registers.svh
++incdir+src/common_cells/include/common_cells/
 src/common_cells/src/fifo_v1.sv
 src/common_cells/src/fifo_v2.sv
 src/common_cells/src/fifo_v3.sv
@@ -25,7 +25,6 @@ src/common_cells/src/rrarbiter.sv
 src/common_cells/src/rstgen_bypass.sv
 src/common_cells/src/sync_wedge.sv
 src/common_cells/src/cdc_2phase.sv
-src/common_cells/src/pipe_reg_simple.sv
 src/common_cells/src/stream_arbiter_flushable.sv
 src/common_cells/src/shift_reg.sv
 src/fpu/src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv
@@ -37,6 +36,7 @@ src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
 src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
 src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
 src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+src/fpu/src/fpnew_pkg.sv
 src/fpu/src/fpnew_cast_multi.sv
 src/fpu/src/fpnew_classifier.sv
 src/fpu/src/fpnew_divsqrt_multi.sv
@@ -55,7 +55,7 @@ src/fpu/src/fpnew_pkg.sv
 src/fpu/src/fpnew_rounding.sv
 src/fpu/src/fpnew_top.sv
 src/axi/src/axi_pkg.sv
-src/debug/dm_pkg.sv
+src/riscv-dbg/src/dm_pkg.sv
 include/riscv_pkg.sv
 include/ariane_pkg.sv
 include/ariane_axi_pkg.sv
@@ -129,7 +129,8 @@ src/riscv-dbg/src/dmi_jtag_tap.sv
 src/riscv-dbg/debug_rom/debug_rom.sv
 openpiton/ariane_verilog_wrap.sv
 openpiton/serpent_peripherals.sv
-openpiton/bootrom/bootrom.sv
+openpiton/bootrom/baremetal/bootrom.sv
+openpiton/bootrom/linux/bootrom_linux.sv
 src/plic/plic.sv
 src/plic/plic_claim_complete_tracker.sv
 src/plic/plic_comparator.sv

include/ariane_pkg.sv

@@ -61,9 +61,22 @@ package ariane_pkg;
     localparam int unsigned DEPTH_COMMIT = 8;
 `endif
 
+
+`ifdef PITON_ARIANE
+`ifdef AXI64_CACHE_PORTS
+    // Floating-point extensions configuration
+    localparam bit RVF = 1'b1; // Is F extension enabled
+    localparam bit RVD = 1'b1; // Is D extension enabled
+`else 
+    // Floating-point extensions configuration
+    localparam bit RVF = 1'b0; // Is F extension enabled
+    localparam bit RVD = 1'b0; // Is D extension enabled
+`endif
+`else 
     // Floating-point extensions configuration
     localparam bit RVF = 1'b1; // Is F extension enabled
     localparam bit RVD = 1'b1; // Is D extension enabled
+`endif
     localparam bit RVA = 1'b1; // Is A extension enabled
 
     // Transprecision floating-point extensions configuration

include/serpent_cache_pkg.sv

@@ -33,8 +33,8 @@ package serpent_cache_pkg;
 `endif
 
 `ifndef L15_THREADID_WIDTH
-    // this results in 4 pending tx slots in the writebuffer
-    `define L15_THREADID_WIDTH 2
+    // this results in 8 pending tx slots in the writebuffer
+    `define L15_THREADID_WIDTH 3
 `endif
 
 `ifndef TLB_CSM_WIDTH

openpiton/bootrom/.gitignore

@@ -1,3 +1,4 @@
 *.elf
 *.img
 *.dtb
+*.sv

openpiton/bootrom/baremetal/.gitignore

@@ -0,0 +1,5 @@
+*.elf
+*.img
+*.dtb
+*.sv
+*.h

openpiton/bootrom/baremetal/Makefile

@@ -0,0 +1 @@
+../../../bootrom/Makefile

openpiton/bootrom/baremetal/ariane.dts

@@ -0,0 +1 @@
+../ariane.dts

openpiton/bootrom/baremetal/bootrom.S

@@ -0,0 +1 @@
+../../../bootrom/bootrom.S

openpiton/bootrom/baremetal/gen_rom.py

@@ -0,0 +1 @@
+../../../bootrom/gen_rom.py

openpiton/bootrom/baremetal/linker.ld

@@ -0,0 +1 @@
+../../../bootrom/linker.ld