Improve Tandem Simulation, switch-able caches and fix a cache-bug (op…

…enhwgroup#192)

* Add spike isa sim

* Fix AMO problem in verilator

* 🎨 Tidy up FPU wrapper

* Bump axi_exclusive submodule

* Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (openhwgroup#190)

* Refactor serpent AXI adapter

* Disable FPU in OpenPiton by default

* Bump dbg and atomics submodules

* Fix cache testbenches (interface change)

* FPGA bootrom changes for OpenPiton SDHC

* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD

* Testing barrier-based synchronisation instead of CLINT-based

* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707

* Add MAX_HARTS switch to makefile

* Fix gitlab CI

* Revert standard FPGA bootrom

* Update Flist

* Make UART_FREQ a parameter

* Fix typo in tb.list and an error in define switch in ariane_pkg

* Copy over SD-driver in bootloader from @leon575777642

* Fix compilation issues of bootrom

* Change signal name in serpent periph portlist

* Correct generate statement in serpent dcache memory

* Add Piton SD Controller, FPGA fixes

* Fix race condition in dcache misshandler

* Add tandem spike to Make flow

* Remove OpenPiton SD Card controller again

CHANGELOG.md

@@ -11,6 +11,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Official support for floating point unit
 - Added AXI-64bit adapter for write-through cache system
 - Added AXI atomic ops and exclusive access support to write-through cache system
+- Provision `riscv-isa-sim` tandem simulation
+- Support for preloading
 
 ### Changed
 
@@ -19,6 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Fixed problem which decoded compressed hints as illegal instructions
 - Reduce clock frequency of FPGA to 30 MHz to accomodate FPU
 - Bugfixes in write-through cache system
+- ID width fix in random delayer
 
 ### 4.0.0
 

Makefile

@@ -41,20 +41,28 @@ ifndef RISCV
 $(error RISCV not set - please point your RISCV variable to your RISCV installation)
 endif
 
+# spike tandem verification
+ifdef spike-tandem
+    compile_flag += -define SPIKE_TANDEM
+    ifndef preload
+        $(error Tandem verification requires preloading)
+    endif
+endif
+
 # Sources
 # Package files -> compile first
 ariane_pkg := include/riscv_pkg.sv                          \
-			        src/riscv-dbg/src/dm_pkg.sv                   \
-			        include/ariane_pkg.sv                         \
-			        include/std_cache_pkg.sv                      \
-			        include/serpent_cache_pkg.sv                  \
-			        src/axi/src/axi_pkg.sv                        \
-			        src/register_interface/src/reg_intf.sv        \
-			        include/axi_intf.sv                           \
-			        tb/ariane_soc_pkg.sv                          \
-			        include/ariane_axi_pkg.sv                     \
-			        src/fpu/src/fpnew_pkg.sv                      \
-			        src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+			  src/riscv-dbg/src/dm_pkg.sv                   \
+			  include/ariane_pkg.sv                         \
+			  include/std_cache_pkg.sv                      \
+			  include/serpent_cache_pkg.sv                  \
+			  src/axi/src/axi_pkg.sv                        \
+			  src/register_interface/src/reg_intf.sv        \
+			  include/axi_intf.sv                           \
+			  tb/ariane_soc_pkg.sv                          \
+			  include/ariane_axi_pkg.sv                     \
+			  src/fpu/src/fpnew_pkg.sv                      \
+			  src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
 ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
 
 # utility modules
@@ -64,18 +72,34 @@ util := $(wildcard src/util/*.svh)                          \
         src/tech_cells_generic/src/cluster_clock_gating.sv  \
         tb/common/mock_uart.sv                              \
         src/util/sram.sv
+
+ifdef spike-tandem
+    util += tb/common/spike.sv
+endif
+
 util := $(addprefix $(root-dir), $(util))
 # Test packages
 test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
 			$(wildcard tb/test/*/*_pkg.sv*)
 # DPI
-dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc))
+dpi_list := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
+# filter spike stuff if tandem is not activated
+ifndef spike-tandem
+    dpi = $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi_list))
+else
+    dpi = $(dpi_list)
+endif
+
 dpi_hdr := $(wildcard tb/dpi/*.h)
 dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
 CFLAGS := -I$(QUESTASIM_HOME)/include         \
           -I$(RISCV)/include                  \
           -std=c++11 -I../tb/dpi
 
+ifdef spike-tandem
+    CFLAGS += -Itb/riscv-isa-sim/install/include/spike
+endif
+
 # this list contains the standalone components
 src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         $(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv))   \
@@ -198,12 +222,12 @@ endif
 ifdef preload
 	questa-cmd += +PRELOAD=$(preload)
 	elf-bin = none
-	# tandem verify with spike, this requires pre-loading
-	ifdef tandem
-		compile_flag += +define+TANDEM
-		questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
-	endif
 endif
+
+ifdef spike-tandem
+    questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
+endif
+
 # remote bitbang is enabled
 ifdef rbb
 	questa-cmd += +jtag_rbb_enable=1
@@ -252,7 +276,7 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
 # alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
 sim: build
 	vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
-	+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi        \
+	+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi  \
 	${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
 
 $(riscv-asm-tests): build
@@ -353,7 +377,7 @@ $(addsuffix -verilator,$(riscv-asm-tests)): verilate
 	$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
 
 $(addsuffix -verilator,$(riscv-amo-tests)): verilate
-	$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) 
+	$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
 
 $(addsuffix -verilator,$(riscv-mul-tests)): verilate
 	$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
@@ -425,18 +449,23 @@ check-torture:
 	grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
 	diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
 
+fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
+
 fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(util) $(uart_src)
 	@echo "[FPGA] Generate sources"
 	@echo read_vhdl        {$(uart_src)}    > fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(util)}       >> fpga/scripts/add_sources.tcl
-	@echo read_verilog -sv {$(filter-out bootrom.sv, $(src))} 	   >> fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(fpga_src)}   >> fpga/scripts/add_sources.tcl
 	@echo "[FPGA] Generate Bitstream"
 	cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20"
 
 .PHONY: fpga
 
+build-spike:
+	cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install
+
 clean:
 	rm -rf $(riscv-torture-dir)/output/test*
 	rm -rf $(library)/ $(dpi-library)/ $(ver-library)/

README.md

@@ -291,6 +291,18 @@ $ make
 $ [sudo] make install
 ```
 
+### Memory Preloading
+
+In standard configuration the debug module will take care of loading the memory content. It will also handle communication with `riscv-fesvr`.
+Depending on the scenario this might not be diserable (e.g.: preloading of a large elf or linux boot in simulation). You can use the preload elf flag to specify the path
+to a binary which will be preloaded.
+
+> You will loose all `riscv-fesvr` communcation like sytemcalls and eoc capabilities.
+
+```
+$ make sim preload=elf
+```
+
 <!-- ### Tandem Verification with Spike
 
 ```

bootrom/ariane.dts

@@ -5,9 +5,6 @@
   #size-cells = <2>;
   compatible = "eth,ariane-bare-dev";
   model = "eth,ariane-bare";
-  // chosen {
-  //   stdout-path = "/soc/uart@10000000:115200";
-  // };
   cpus {
     #address-cells = <1>;
     #size-cells = <0>;
@@ -31,7 +28,7 @@
   };
   memory@80000000 {
     device_type = "memory";
-    reg = <0x0 0x80000000 0x0 0x1800000>;
+    reg = <0x0 0x80000000 0x0 0x10000000>;
   };
   soc {
     #address-cells = <2>;
@@ -44,16 +41,17 @@
       reg = <0x0 0x2000000 0x0 0xc0000>;
       reg-names = "control";
     };
-    PLIC0: interrupt-controller@c000000 {
-      #address-cells = <0>;
-      #interrupt-cells = <1>;
-      compatible = "sifive,plic-1.0.0", "riscv,plic0";
-      interrupt-controller;
-      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-      reg = <0x0 0xc000000 0x0 0x4000000>;
-      riscv,max-priority = <7>;
-      riscv,ndev = <2>;
-    };
+    // PLIC needs to be disabeld for tandem verification
+    // PLIC0: interrupt-controller@c000000 {
+    //   #address-cells = <0>;
+    //   #interrupt-cells = <1>;
+    //   compatible = "sifive,plic-1.0.0", "riscv,plic0";
+    //   interrupt-controller;
+    //   interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+    //   reg = <0x0 0xc000000 0x0 0x4000000>;
+    //   riscv,max-priority = <7>;
+    //   riscv,ndev = <2>;
+    // };
     debug-controller@0 {
       compatible = "riscv,debug-013";
       interrupts-extended = <&CPU0_intc 65535>;
@@ -65,7 +63,7 @@
       reg = <0x0 0x10000000 0x0 0x1000>;
       clock-frequency = <50000000>;
       current-speed = <115200>;
-      interrupt-parent = <&PLIC0>;
+      // interrupt-parent = <&PLIC0>;
       interrupts = <1>;
       reg-shift = <2>; // regs are spaced on 32 bit boundary
       reg-io-width = <4>; // only 32-bit access are supported