Add System Verilog FPU (openhwgroup#163)

* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals. * saving... * ⬆️ Updates for new FPU * Add sv fpu to FPGA flow * Use multi-threading capabilities of verilator - Deactivate non-standard floating point arguments - Make multi-threading conditional on the availability of verilator 4 * Remove DPI threadsafety * Reduce FPGA clock frequency - Remove couple of -v- tests to reduce test-time * Fix documentation and fpga flow - Fix cycle time to accommodate FPU - Fix FPGA constraints * Change UART frequency
msfschaffner · Mar 18, 2019 · b1bdc0c · b1bdc0c
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -11,6 +11,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Changed
 
 - Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board
+- Increase available RAM size on Genesys II board to 1 GiB
+- Fixed problem which decoded compressed hints as illegal instructions
+- Reduce clock frequency of FPGA to 30 MHz to accomodate FPU
+- Official support for floating point unit
 
 ### 4.0.0
 

diff --git a/Makefile b/Makefile
diff --git a/README.md b/README.md
@@ -15,7 +15,6 @@ Table of Contents
    * [Table of Contents](#table-of-contents)
       * [Getting Started](#getting-started)
          * [Running User-Space Applications](#running-user-space-applications)
-         * [FPU Support](#fpu-support)
       * [FPGA Emulation](#fpga-emulation)
          * [Programming the Memory Configuration File](#programming-the-memory-configuration-file)
          * [Preparing the SD Card](#preparing-the-sd-card)
@@ -102,10 +101,6 @@ $ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf  b
 
 > Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
 
-### FPU Support
-
-> There is preliminary support for floating point extensions F and D. At the moment floating point support will only be available in QuestaSim as the FPU is written in VHDL. This is likely to change. The floating point extensions can be enabled by setting `RVF` and `RVD` to `1'b1` in the `include/ariane_pkg.sv` file.
-
 ## FPGA Emulation
 
 We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/pulp-platform/ariane/releases).
@@ -168,7 +163,6 @@ To get started, connect the micro USB port that is labeled with JTAG to your mac
 
 Once attached to your system, the FTDI chip should be listed when you type `lsusb`
 
-```
 Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
 ```
 

diff --git a/bootrom/ariane.dts b/bootrom/ariane.dts
@@ -18,7 +18,7 @@
       reg = <0>;
       status = "okay";
       compatible = "eth, ariane", "riscv";
-      riscv,isa = "rv64imacsu";
+      riscv,isa = "rv64imafdc";
       mmu-type = "riscv,sv39";
       tlb-split;
       // HLIC - hart local interrupt controller

diff --git a/ci/check-tests.sh b/ci/check-tests.sh
@@ -12,7 +12,7 @@ cd $ROOT
 if [[ -z "$-" ]]; then
   GREEN=''
   RED=''
-  NC='' 
+  NC=''
 else
   GREEN='\033[0;32m'
   RED='\033[0;31m'
@@ -28,7 +28,7 @@ fi
 # get NUM_TOTAL number of tests
 NUM_TOTAL=$2
 
-echo "list containint tests: $2"
+echo "list containing tests: $2"
 
 echo "checking files:"
 ls "${1}"*.log
@@ -45,7 +45,7 @@ echo "NUM_FAILED: $NUM_FAILED"
 echo "NUM_FATAL:  $NUM_FATAL"
 echo "NUM_ERROR:  $NUM_ERROR"
 
-if [[ $(($NUM_FAILED)) -gt 0 ]]; then 
+if [[ $(($NUM_FAILED)) -gt 0 ]]; then
   echo -e "${RED}FAILED $NUM_FAILED of $NUM_TOTAL tests ${NC}"
   exit 1;
 elif [[ $(($NUM_FATAL)) -ne  0 ]]; then
@@ -60,4 +60,4 @@ elif [[ $(($NUM_PASSED)) -ne $(($NUM_TOTAL)) ]]; then
 else
   echo -e "${GREEN}PASSED all $NUM_TOTAL tests ${NC}"
   exit 0;
-fi    
+fi
diff --git a/ci/float.config b/ci/float.config
@@ -0,0 +1,52 @@
+torture.generator.nseqs     1000
+torture.generator.memsize   1024
+torture.generator.fprnd     0
+torture.generator.amo       false
+torture.generator.mul       true
+torture.generator.divider   true
+torture.generator.segment   true
+torture.generator.loop	    true
+torture.generator.loop_size 64
+
+torture.generator.mix.xmem    15
+torture.generator.mix.xbranch 25
+torture.generator.mix.xalu    15
+torture.generator.mix.fgen    20
+torture.generator.mix.fpmem   10
+torture.generator.mix.fax     10
+torture.generator.mix.fdiv    5
+torture.generator.mix.vec     0
+
+torture.generator.vec.vf 1
+torture.generator.vec.seq 20
+torture.generator.vec.memsize 128
+torture.generator.vec.numsregs 64
+torture.generator.vec.mul false
+torture.generator.vec.div false
+torture.generator.vec.mix true
+torture.generator.vec.fpu false
+torture.generator.vec.fma false
+torture.generator.vec.fcvt false
+torture.generator.vec.fdiv false
+torture.generator.vec.amo false
+torture.generator.vec.seg false
+torture.generator.vec.stride false
+torture.generator.vec.pred_alu true
+torture.generator.vec.pred_mem true
+
+torture.generator.vec.mix.valu  20
+torture.generator.vec.mix.vpop  60
+torture.generator.vec.mix.vmem  20
+torture.generator.vec.mix.vonly 0
+
+torture.testrun.maxcycles 10000000
+torture.testrun.virtual   false
+torture.testrun.seek      true
+torture.testrun.dump      false
+torture.testrun.vec       false
+
+torture.overnight.errors  1
+torture.overnight.minutes 1
+torture.overnight.outdir  output/failedtests
+torture.overnight.email   [email protected]
+
diff --git a/ci/install-verilator.sh b/ci/install-verilator.sh
@@ -9,14 +9,15 @@ fi
 
 if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then
     echo "Installing Verilator"
-    wget https://www.veripool.org/ftp/verilator-3.924.tgz
-    tar xzf verilator*.t*gz 
-    rm verilator*.t*gz 
+    rm verilator*.t*gz
+    wget https://www.veripool.org/ftp/verilator-4.008.tgz
+    tar xzf verilator*.t*gz
+    rm verilator*.t*gz
     cd verilator-*
     mkdir -p $VERILATOR_ROOT
     # copy scripts
-    autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} 
-    cp -r * $VERILATOR_ROOT/ 
+    autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS}
+    cp -r * $VERILATOR_ROOT/
     make test
 else
     echo "Using Verilator from cached directory."

diff --git a/ci/path-setup.sh b/ci/path-setup.sh
@@ -5,12 +5,12 @@ export CI_BUILD_DIR=$TOP/ariane-repo
 #customize this to your setup
 export QUESTASIM_HOME=
 export QUESTASIM_VERSION=
-export QUESTASIM_FLAGS=-noautoldlibpath
+export QUESTASIM_FLAGS=
 export CXX=g++-7 CC=gcc-7
 
 # where to install the tools
 export RISCV=$TOP/riscv_install
-export VERILATOR_ROOT=$TOP/verilator-3.924/
+export VERILATOR_ROOT=$TOP/verilator-4.008/
 
 export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
 export LIBRARY_PATH=$RISCV/lib
@@ -19,4 +19,4 @@ export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
 export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
 
 # number of parallel jobs to use for make commands and simulation
-export NUM_JOBS=8
+export NUM_JOBS=8
diff --git a/ci/riscv-asm-tests.list b/ci/riscv-asm-tests.list
@@ -78,26 +78,6 @@ rv64ui-v-or
 rv64ui-v-ori
 rv64ui-v-sub
 rv64ui-v-subw
-rv64ui-v-xor
-rv64ui-v-xori
 rv64ui-v-sll
 rv64ui-v-slli
-rv64ui-v-slliw
-rv64ui-v-slt
-rv64ui-v-slti
-rv64ui-v-sltiu
-rv64ui-v-sltu
-rv64ui-v-sra
-rv64ui-v-srai
-rv64ui-v-sraiw
-rv64ui-v-sraw
-rv64ui-v-srl
-rv64ui-v-srli
-rv64ui-v-srliw
-rv64ui-v-srlw
 rv64ui-v-lb
-rv64ui-v-lbu
-rv64ui-v-ld
-rv64ui-v-lh
-rv64ui-v-lhu
-rv64ui-v-lui
diff --git a/ci/riscv-fp-tests.list b/ci/riscv-fp-tests.list
@@ -0,0 +1,38 @@
+rv64uf-p-fadd
+rv64uf-p-fclass
+rv64uf-p-fcmp
+rv64uf-p-fcvt
+rv64uf-p-fcvt_w
+rv64uf-p-fdiv
+rv64uf-p-fmadd
+rv64uf-p-fmin
+rv64uf-p-ldst
+rv64uf-p-move
+rv64uf-p-recoding
+rv64uf-v-fadd
+rv64uf-v-fclass
+rv64uf-v-fcmp
+rv64uf-v-fcvt
+rv64uf-v-fcvt_w
+rv64uf-v-fdiv
+rv64uf-v-fmadd
+rv64uf-v-fmin
+rv64uf-v-ldst
+rv64uf-v-move
+rv64uf-v-recoding
+rv64ud-p-fadd
+rv64ud-p-fclass
+rv64ud-p-fcmp
+rv64ud-p-fcvt
+rv64ud-p-fcvt_w
+rv64ud-p-fdiv
+rv64ud-p-fmadd
+rv64ud-p-fmin
+rv64ud-v-fadd
+rv64ud-v-fclass
+rv64ud-v-fcmp
+rv64ud-v-fcvt
+rv64ud-v-fcvt_w
+rv64ud-v-fdiv
+rv64ud-v-fmadd
+rv64ud-v-fmin
diff --git a/fpga/constraints/ariane.xdc b/fpga/constraints/ariane.xdc
@@ -3,10 +3,10 @@
 create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
 set_input_jitter tck 1.000
 
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 10.000
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 10.000
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 10.000
-
-
-
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
 
+# set multicycle path on reset, on the FPGA we do not care about the reset anyway
+set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
+set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3  -hold
diff --git a/fpga/constraints/genesys-2.xdc b/fpga/constraints/genesys-2.xdc
@@ -1,22 +1,12 @@
 ## Buttons
 set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
 
-## PMOD Header JC
-# set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck]
-# set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi]
-# set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo]
-# set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms]
-# set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n]
-# accept sub-optimal placement
-# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
-
-
 ## To use FTDI FT2232 JTAG
-set_property -dict { PACKAGE_PIN Y29   IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; 
-set_property -dict { PACKAGE_PIN AD27  IOSTANDARD LVCMOS33 } [get_ports { tck    }]; 
-set_property -dict { PACKAGE_PIN W27   IOSTANDARD LVCMOS33 } [get_ports { tdi    }]; 
-set_property -dict { PACKAGE_PIN W28   IOSTANDARD LVCMOS33 } [get_ports { tdo    }]; 
-set_property -dict { PACKAGE_PIN W29   IOSTANDARD LVCMOS33 } [get_ports { tms    }]; 
+set_property -dict { PACKAGE_PIN Y29   IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
+set_property -dict { PACKAGE_PIN AD27  IOSTANDARD LVCMOS33 } [get_ports { tck    }];
+set_property -dict { PACKAGE_PIN W27   IOSTANDARD LVCMOS33 } [get_ports { tdi    }];
+set_property -dict { PACKAGE_PIN W28   IOSTANDARD LVCMOS33 } [get_ports { tdo    }];
+set_property -dict { PACKAGE_PIN W29   IOSTANDARD LVCMOS33 } [get_ports { tms    }];
 
 ## UART
 set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx]
@@ -72,7 +62,8 @@ set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio
 #############################################
 # Modified for 125MHz receive clock
 create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
-set_clock_groups -asynchronous -group [get_clocks eth_rxclk -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
 
 ## SD Card
 set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
@@ -85,13 +76,12 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
 
 ## JTAG
 # minimize routing delay
-set_max_delay -to   [get_ports { td    } ] 5 
-set_max_delay -from [get_ports { tms   } ] 5 
-set_max_delay -from [get_ports { trst_n } ] 5
 
-# reset signal 
-set_false_path -from [get_ports { trst_n } ]
+set_max_delay -to   [get_ports { tdo } ] 20
+set_max_delay -from [get_ports { tms } ] 20
+set_max_delay -from [get_ports { tdi } ] 20
+set_max_delay -from [get_ports { trst_n } ] 20
 
-# constrain clock domain crossing
-set_false_path -from [get_clocks tck] -to [get_clocks clk_out1]
-set_max_delay  -from [get_clocks tck] -to [get_clocks clk_out1] 5
+# reset signal
+set_false_path -from [get_ports { trst_n } ]
+set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/scripts/prologue.tcl b/fpga/scripts/prologue.tcl
@@ -22,4 +22,6 @@ set_property board_part $::env(XILINX_BOARD) [current_project]
 # set number of threads to 8 (maximum, unfortunately)
 set_param general.maxThreads 8
 
-set_msg_config -id {[Synth 8-5858]}         -new_severity "info"
+set_msg_config -id {[Synth 8-5858]} -new_severity "info"
+
+set_msg_config -id {[Synth 8-4480]} -limit 1000
diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl
@@ -29,13 +29,14 @@ source scripts/add_sources.tcl
 set_property top ${project}_xilinx [current_fileset]
 
 if {$::env(BOARD) eq "genesys2"} {
-    read_verilog -sv {src/genesysii.svh}
+    read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
     set file "src/genesysii.svh"
+    set registers "../src/common_cells/include/common_cells/registers.svh"
 } else {
     exit 1
 }
 
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
 set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
 
 update_compile_order -fileset sources_1
@@ -46,6 +47,8 @@ add_files -fileset constrs_1 -norecurse constraints/$project.xdc
 # synth_design -retiming -rtl -name rtl_1 -verilog_define SYNTHESIS -verilog_define
 synth_design -rtl -name rtl_1
 
+set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
+
 launch_runs synth_1
 wait_on_run synth_1
 open_run synth_1

diff --git a/fpga/src/bootrom/ariane.dts b/fpga/src/bootrom/ariane.dts
@@ -13,12 +13,12 @@
     #size-cells = <0>;
     timebase-frequency = <25000000>; // 25 MHz
     CPU0: cpu@0 {
-      clock-frequency = <50000000>; // 50 MHz
+      clock-frequency = <30000000>; // 30 MHz
       device_type = "cpu";
       reg = <0>;
       status = "okay";
       compatible = "eth, ariane", "riscv";
-      riscv,isa = "rv64imacsu";
+      riscv,isa = "rv64imafdc";
       mmu-type = "riscv,sv39";
       tlb-split;
       // HLIC - hart local interrupt controller
@@ -71,7 +71,7 @@
     uart@10000000 {
       compatible = "ns16750";
       reg = <0x0 0x10000000 0x0 0x1000>;
-      clock-frequency = <50000000>;
+      clock-frequency = <30000000>;
       current-speed = <115200>;
       interrupt-parent = <&PLIC0>;
       interrupts = <1>;