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Merge 7c41afb on remote branch
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Change-Id: Ia254647e749d387f6ba37f80dc9f656b12da621f
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Linux Build Service Account committed Mar 2, 2023
2 parents 2a30c59 + 7c41afb commit 24aeab8
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Showing 5 changed files with 29 additions and 6 deletions.
4 changes: 4 additions & 0 deletions msm/dsi/dsi_ctrl.c
Original file line number Diff line number Diff line change
Expand Up @@ -3076,6 +3076,8 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
return -EINVAL;
}

mutex_lock(&dsi_ctrl->ctrl_lock);

if (dsi_ctrl->hw.ops.host_setup)
dsi_ctrl->hw.ops.host_setup(&dsi_ctrl->hw,
&dsi_ctrl->host_config.common_config);
Expand All @@ -3093,9 +3095,11 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl)
0x0, NULL);
} else {
DSI_CTRL_ERR(dsi_ctrl, "invalid panel mode for resolution switch\n");
mutex_unlock(&dsi_ctrl->ctrl_lock);
return -EINVAL;
}

mutex_unlock(&dsi_ctrl->ctrl_lock);
return 0;
}

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6 changes: 6 additions & 0 deletions msm/dsi/dsi_display.c
Original file line number Diff line number Diff line change
Expand Up @@ -3558,6 +3558,12 @@ static int dsi_display_clocks_init(struct dsi_display *display)

num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);

if (num_clk <= 0) {
rc = num_clk;
DSI_WARN("failed to read %s, rc = %d\n", dsi_clock_name, num_clk);
goto error;
}

DSI_DEBUG("clk count=%d\n", num_clk);

for (i = 0; i < num_clk; i++) {
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8 changes: 7 additions & 1 deletion msm/sde/sde_crtc.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <[email protected]>
Expand Down Expand Up @@ -3323,6 +3323,12 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
_sde_crtc_blend_setup(crtc, old_state, true);
_sde_crtc_dest_scaler_setup(crtc);

/* cancel the idle notify delayed work */
if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
MSM_DISPLAY_VIDEO_MODE) &&
kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
SDE_DEBUG("idle notify work cancelled\n");

if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)
sde_core_perf_crtc_update_uidle(crtc, true);

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12 changes: 10 additions & 2 deletions msm/sde/sde_kms.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <[email protected]>
Expand Down Expand Up @@ -3907,6 +3907,7 @@ static int sde_kms_pm_suspend(struct device *dev)
DRM_ERROR("failed to get crtc %d state\n",
conn->state->crtc->base.id);
drm_connector_list_iter_end(&conn_iter);
ret = -EINVAL;
goto unlock;
}

Expand Down Expand Up @@ -3945,6 +3946,12 @@ static int sde_kms_pm_suspend(struct device *dev)
drm_modeset_backoff(&ctx);
goto retry;
}

if ((ret || !num_crtcs) && sde_kms->suspend_state) {
drm_atomic_state_put(sde_kms->suspend_state);
sde_kms->suspend_state = NULL;
}

drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);

Expand Down Expand Up @@ -3985,7 +3992,8 @@ static int sde_kms_pm_resume(struct device *dev)

SDE_EVT32(sde_kms->suspend_state != NULL);

drm_mode_config_reset(ddev);
if (sde_kms->suspend_state)
drm_mode_config_reset(ddev);

drm_modeset_acquire_init(&ctx, 0);
retry:
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5 changes: 2 additions & 3 deletions msm/sde_rsc.c
Original file line number Diff line number Diff line change
Expand Up @@ -368,9 +368,8 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc,
rsc_time_slot_0_ns = div_u64(rsc_time_slot_0_ns, cxo_period_ns);
rsc->timer_config.rsc_time_slot_0_ns = (u32) rsc_time_slot_0_ns;

/* time_slot_1 for mode1 latency */
rsc_time_slot_1_ns = frame_time_ns;
rsc_time_slot_1_ns = div_u64(rsc_time_slot_1_ns, cxo_period_ns);
/* time_slot_1 for mode1 latency - 1 fps */
rsc_time_slot_1_ns = div_u64(TICKS_IN_NANO_SECOND, cxo_period_ns);
rsc->timer_config.rsc_time_slot_1_ns = (u32) rsc_time_slot_1_ns;

/* mode 2 is infinite */
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