initial add

runtime/src/iree-amd-aie/aie_runtime/iree_aie_configure.cc

@@ -20,6 +20,11 @@
 
 using Path = std::filesystem::path;
 
+extern "C" {
+#include "xaie_hwcfg.h"
+#include "xaiengine.h"
+}
+
 namespace mlir::iree_compiler::AMDAIE {
 
 FailureOr<XAie_DmaDesc> initDMADesc(const AMDAIEDeviceModel &deviceModel,

runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc

@@ -14,6 +14,7 @@
 
 extern "C" {
 #include "xaiengine.h"
+#include "xaie_hwcfg.h"
 #undef s8
 #undef u8
 #undef u16
@@ -168,6 +169,7 @@ int AMDAIEDeviceModel::rows() const {
     return MLIRAIELegacy::rows(*this);
   assert(isNPUDevice(device) && "expected NPU device");
   return devInst.NumRows;
+
 }
 
 int AMDAIEDeviceModel::columns() const {

runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h

@@ -8,23 +8,16 @@
 #define IREE_AIE_RUNTIME_H
 
 #include <optional>
-#include <ostream>
-#include <sstream>
 #include <tuple>
 #include <type_traits>
 
+#include "iree-amd-aie/aie_runtime/AMDAIEEnums.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/FormattedStream.h"
 #include "macros.h"
-// clang-format off
-#include "iree-amd-aie/aie_runtime/AMDAIEEnums.h"
-// clang-format on
 
 extern "C" {
-#include "xaie_hwcfg.h"
 #include "xaiengine.h"
-#include "xaiengine/xaie_device_aieml.h"
 #undef s8
 #undef u8
 #undef u16
@@ -204,7 +197,9 @@ enum class AIEArch : uint8_t { AIE1 = 1, AIE2 = 2 };
  * This struct is meant to be a thin wrapper around aie-rt, which provides
  * the canonical representation/metadata for AIE devices; attributes like number
  * of locks, bds per tile, whether certain switch connections are legal or not,
- * etc.
+ * etc. In addition this struct is meant to contain generational specific AIE
+ * VLIW processor constants, such as sizes of vectors supported for
+ * load/store/matmul etc.
  *
  * This representation is parameterized by platform specific constants
  * (BASE_ADDR, COL/ROW shift, NUM_MEM_TILE_ROWS, etc.) which are available in
@@ -219,8 +214,9 @@ enum class AIEArch : uint8_t { AIE1 = 1, AIE2 = 2 };
  */
 struct AMDAIEDeviceModel {
   /// Contains additional device config parameters that can't be retrieved from
-  /// aie-rt for whatever reason. Make sure the parameters can't be retrieved in
-  /// another way before adding new fields to this struct.
+  /// aie-rt or elsewhere for whatever reason. Make sure the parameters can't be
+  /// retrieved in another way before adding new fields to this struct.
+
   struct AMDAIEDeviceConfig {
     /// Set default minimum stride bitwidth/addressing granularity to 32 bits as
     /// this is the value for all current architecture versions.
@@ -234,8 +230,26 @@ struct AMDAIEDeviceModel {
     uint8_t streamSwitchMemTileMSelMax{0};
     uint8_t streamSwitchShimArbiterMax{0};
     uint8_t streamSwitchShimMSelMax{0};
+
+    //////////////////////////////
+    // VLIW processor constants //
+    //////////////////////////////
+    /// The number of bits that L1 memory must be aligned by in order
+    /// to be loaded/stored into a register with a vector instruction. See for
+    /// example:
+    /// https://www.xilinx.com/htmldocs/xilinx2024_1/aiengine_ml_intrinsics/intrinsics/group__intr__loadstore.html
+    uint32_t vectorLoadStoreAlignmentBits{256};
+    /// The largest vector size supported. See for example:
+    /// https://www.xilinx.com/htmldocs/xilinx2024_1/aiengine_ml_intrinsics/intrinsics/group__group__datatype__vector.html
+    uint32_t maxVectorSizeBits{1024};
+    /// The number of bits that each of the two vector operands of the shift
+    /// intrinsic must have. See for example
+    /// https://www.xilinx.com/htmldocs/xilinx2024_1/aiengine_ml_intrinsics/intrinsics/group__intr__gpvectorop__shift.html
+    uint32_t shiftOperandBits{512};
+
     AMDAIEDeviceConfig() = default;
   };
+
   XAie_Config configPtr;
   XAie_DevInst devInst;
   AMDAIEDeviceConfig deviceConfig;
@@ -328,6 +342,14 @@ struct AMDAIEDeviceModel {
   uint8_t getStreamSwitchArbiterMax(uint8_t col, uint8_t row) const;
   uint8_t getStreamSwitchMSelMax(uint8_t col, uint8_t row) const;
 
+  uint32_t getVectorLoadStoreAlignmentBits() const {
+    return deviceConfig.vectorLoadStoreAlignmentBits;
+  }
+
+  uint32_t getMaxVectorSizeBits() const { return deviceConfig.maxVectorSizeBits; }
+
+  uint32_t getShiftOperandBits() const { return deviceConfig.shiftOperandBits; }
+
   /// Return a map from channels to valid BD ids for the requested tile type.
   /// TODO(jornt): find these ranges in the device model.
   DenseMap<uint32_t, SmallVector<uint32_t>> getChannelToValidBdIds(

runtime/src/iree-amd-aie/aie_runtime/test/test_control_packets.cc

@@ -47,7 +47,7 @@ clang-format on
 #include <cstdio>
 
 #include "interpreter_op_impl.h"
-#include "iree-amd-aie/aie_runtime/iree_aie_runtime.h"
+#include "iree-amd-aie/aie_runtime/xaie_hwcfg.h"
 
 #define DATA_SIZE 17
 #define WRRD_DATA_SIZE 0x02

runtime/src/iree-amd-aie/aie_runtime/test/test_packet_switch_mode.cc

@@ -129,7 +129,7 @@ clang-format on
 #include <cstdio>
 
 #include "interpreter_op_impl.h"
-#include "iree-amd-aie/aie_runtime/iree_aie_runtime.h"
+#include "iree-amd-aie/aie_runtime/xaie_hwcfg.h"
 
 using namespace mlir::iree_compiler;
 using namespace mlir::iree_compiler::AMDAIE;

runtime/src/iree-amd-aie/aie_runtime/test/test_transaction.cc

@@ -46,6 +46,9 @@ clang-format on
 
 #include "interpreter_op_impl.h"
 #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h"
+#include "iree-amd-aie/aie_runtime/xaie_hwcfg.h"
+
+
 
 using namespace mlir::iree_compiler;
 using namespace mlir::iree_compiler::AMDAIE;

runtime/src/iree-amd-aie/aie_runtime/test/utest.cc

@@ -230,6 +230,7 @@ clang-format off
 #include <string>
 
 #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h"
+#include "iree-amd-aie/aie_runtime/xaie_hwcfg.h"
 
 int main(int argc, char** argv) {
   std::string elfPath(argv[1]);