Add width-agnostic serv_rf_ram_if

rtl/serv_rf_ram_if.v

@@ -3,6 +3,7 @@ module serv_rf_ram_if
   #(//Data width. Adjust to preferred width of SRAM data interface
     parameter width=8,
 
+    parameter W = 1,
     //Select reset strategy.
     // "MINI" for resetting minimally required FFs
     // "NONE" for relying on FFs having a defined value on startup
@@ -13,6 +14,7 @@ module serv_rf_ram_if
     parameter csr_regs=4,
 
     //Internal parameters calculated from above values. Do not change
+    parameter B=W-1,
     parameter raw=$clog2(32+csr_regs), //Register address width
     parameter l2w=$clog2(width), //log2 of width
     parameter aw=5+raw-l2w) //Address width
@@ -27,12 +29,12 @@ module serv_rf_ram_if
    input wire [raw-1:0]	   i_wreg1,
    input wire		   i_wen0,
    input wire		   i_wen1,
-   input wire		   i_wdata0,
-   input wire		   i_wdata1,
+   input wire [B:0]	   i_wdata0,
+   input wire [B:0]	   i_wdata1,
    input wire [raw-1:0]	   i_rreg0,
    input wire [raw-1:0]	   i_rreg1,
-   output wire		   o_rdata0,
-   output wire		   o_rdata1,
+   output wire [B:0]	   o_rdata0,
+   output wire [B:0]	   o_rdata1,
    //RAM side
    output wire [aw-1:0]	   o_waddr,
    output wire [width-1:0] o_wdata,
@@ -41,19 +43,23 @@ module serv_rf_ram_if
    output wire		   o_ren,
    input wire [width-1:0]  i_rdata);
 
+   localparam ratio = width/W;
+   localparam CMSB = 4-$clog2(W); //Counter MSB
+   localparam l2r  = $clog2(ratio);
+
    reg 				   rgnt;
    assign o_ready = rgnt | i_wreq;
-   reg [4:0] 	  rcnt;
+   reg [CMSB:0] 	  rcnt;
 
    reg 		  rtrig1;
    /*
     ********** Write side ***********
     */
 
-   wire [4:0] 	     wcnt;
+   wire [CMSB:0] 	     wcnt;
 
    reg [width-1:0]   wdata0_r;
-   reg [width-0:0]   wdata1_r;
+   reg [width+W-1:0]   wdata1_r;
 
    reg 		     wen0_r;
    reg 		     wen1_r;
@@ -62,9 +68,9 @@ module serv_rf_ram_if
 
    assign wtrig0 = rtrig1;
 
-   generate if (width == 2) begin : gen_w_eq_2
+   generate if (ratio == 2) begin : gen_wtrig_ratio_eq_2
       assign wtrig1 =  wcnt[0];
-   end else begin : gen_w_neq_2
+   end else begin : gen_wtrig_ratio_neq_2
       reg wtrig0_r;
       always @(posedge i_clk) wtrig0_r <= wtrig0;
       assign wtrig1 = wtrig0_r;
@@ -79,7 +85,7 @@ module serv_rf_ram_if
    generate if (width == 32) begin : gen_w_eq_32
       assign o_waddr = wreg;
    end else begin : gen_w_neq_32
-      assign o_waddr = {wreg, wcnt[4:l2w]};
+      assign o_waddr = {wreg, wcnt[CMSB:l2r]};
    end
    endgenerate
 
@@ -93,8 +99,8 @@ module serv_rf_ram_if
 	 wen1_r    <= i_wen1;
       end
 
-      wdata0_r  <= {i_wdata0,wdata0_r[width-1:1]};
-      wdata1_r  <= {i_wdata1,wdata1_r[width-0:1]};
+      wdata0_r  <= {i_wdata0,wdata0_r[width-1:W]};
+      wdata1_r  <= {i_wdata1,wdata1_r[width+W-1:W]};
 
    end
 
@@ -109,37 +115,37 @@ module serv_rf_ram_if
    generate if (width == 32) begin : gen_rreg_eq_32
       assign o_raddr = rreg;
    end else begin : gen_rreg_neq_32
-      assign o_raddr = {rreg, rcnt[4:l2w]};
+      assign o_raddr = {rreg, rcnt[CMSB:l2r]};
    end
    endgenerate
 
    reg [width-1:0]  rdata0;
-   reg [width-2:0]  rdata1;
+   reg [width-1-W:0]  rdata1;
 
    reg 		    rgate;
 
-   assign o_rdata0 = rdata0[0];
-   assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0];
+   assign o_rdata0 = rdata0[B:0];
+   assign o_rdata1 = rtrig1 ? i_rdata[B:0] : rdata1[B:0];
 
-   assign rtrig0 = (rcnt[l2w-1:0] == 1);
+   assign rtrig0 = (rcnt[l2r-1:0] == 1);
 
-   generate if (width == 2) begin : gen_ren_w_eq_2
+   generate if (ratio == 2) begin : gen_ren_w_eq_2
       assign o_ren = rgate;
    end else begin : gen_ren_w_neq_2
-      assign o_ren = rgate & (rcnt[l2w-1:1] == 0);
+      assign o_ren = rgate & (rcnt[l2r-1:1] == 0);
    end
    endgenerate
 
    reg 	      rreq_r;
 
-   generate if (width>2) begin : gen_rdata1_w_neq_2
+   generate if (ratio > 2) begin : gen_rdata1_w_neq_2
       always @(posedge i_clk) begin
-	 rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize?
+	 rdata1 <= {{W{1'b0}},rdata1[width-W-1:W]};
 	 if (rtrig1)
-	   rdata1[width-2:0] <= i_rdata[width-1:1];
+	   rdata1[width-W-1:0] <= i_rdata[width-1:W];
       end
    end else begin : gen_rdata1_w_eq_2
-      always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1];
+      always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[W*2-1:W];
    end
    endgenerate
 
@@ -148,14 +154,14 @@ module serv_rf_ram_if
 	rgate <= i_rreq;
 
       rtrig1 <= rtrig0;
-      rcnt <= rcnt+5'd1;
+      rcnt <= rcnt+{{CMSB{1'b0}},1'b1};
       if (i_rreq | i_wreq)
-	 rcnt <= {3'd0,i_wreq,1'b0};
+	 rcnt <= {{CMSB-1{1'b0}},i_wreq,1'b0};
 
       rreq_r <= i_rreq;
       rgnt <= rreq_r;
 
-      rdata0 <= {1'b0,rdata0[width-1:1]};
+      rdata0 <= {{W{1'b0}}, rdata0[width-1:W]};
       if (rtrig0)
 	rdata0 <= i_rdata;
 
@@ -164,7 +170,7 @@ module serv_rf_ram_if
 	    rgate <= 1'b0;
 	    rgnt <= 1'b0;
 	    rreq_r <= 1'b0;
-	    rcnt <= 5'd0;
+	    rcnt <= {CMSB+1{1'b0}};
 	 end
       end
    end