wip

olofk · Oct 1, 2024 · cf4b4ea · cf4b4ea
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diff --git a/doc/datasheet.rst b/doc/datasheet.rst
@@ -2,4 +2,5 @@
 Datasheet
 *********
 
+.. include:: overview.rst
 .. include:: interface.rst
diff --git a/doc/overview.rst b/doc/overview.rst
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+Interface
+=========
+
+The SERV RISC-V CPU is an award-winning and highly compact processor core based on the RISC-V instruction set architecture (ISA). It is designed to be the smallest possible RISC-V compliant CPU and is particularly well-suited for embedded systems and applications where silicon area is critical.