Change timer wraparound behavior to be more useful

[alinja]

Risc-v timer is specified to be 64 bits long, meaning wraparound times of hundreds or thousands of years, making wraparound practically a non-issue. Servant has 32-bit timer, and it is not useful then timer wraps around. To avoid actually using 64 bits, this makes the timer useful even when the timer wraps around.

[olofk]

Thank you for your contribution. I trust that this is an improvement, but I'm terrible at Verilog math, so would you mind quickly explaining what the actual difference is? Been staring at the code and can't for my life understand why this is better :)

[alinja]

Current unsigned comparison has a wraparound period of about 30s with 125MHz clock. When the mtime is near its maximum and a timer irq is requested after even a small time in future, mtimecmp will wrap around and an interrupt is generated immediately.

With signed comparison like this, the interrupt is generated at the right time, because the difference is positive even when crossing the wraparound boundary. Only downside is that interrupts can only be requested 15s in advance.

[olofk]

Aha! I think I understand. All good. Thanks for the explanation. Picked and pushed!