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cpu: aarch64: fix jit_brgemm warnings #2118

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merged 2 commits into from
Sep 25, 2024
+21 −11
Merged

cpu: aarch64: fix jit_brgemm warnings #2118

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0f9e6c9
aarch64: fix jit_brgemm warnings
taoye9 Sep 24, 2024
738c3c3
aarch64: fix out-of-bound warnings of deconvolution
taoye9 Sep 25, 2024
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8 changes: 6 additions & 2 deletions src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*******************************************************************************
* Copyright 2021-2023 Intel Corporation
* Copyright 2024 FUJITSU LIMITED
* Copyright 2024 Arm Ltd. and affiliates
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -1876,15 +1877,18 @@ void jit_brgemm_kernel_t::bdb_loop() {
}

void jit_brgemm_kernel_t::generate() {
size_t simd_w_;
size_t simd_w_ = 0;
switch (brg.isa_impl) {
case sve_512:
simd_w_ = cpu_isa_traits<sve_512>::vlen / sizeof(float);
break;
case sve_256:
simd_w_ = cpu_isa_traits<sve_256>::vlen / sizeof(float);
break;
default: assert(!"unsupported isa");
default: {
assert(!"unsupported isa");
return;
}
}
preamble();
if (simd_w_ != cpu_sveLen / sizeof(float)) {
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/aarch64/jit_brgemm_conv_comp_pad_kernel.hpp
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*******************************************************************************
* Copyright 2022-2023 Intel Corporation
* Copyright 2024 FUJITSU LIMITED
* Copyright 2024 Arm Ltd. and affiliates
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -43,8 +44,7 @@ struct jit_uni_brgemm_conv_comp_pad_kernel_t : public jit_generator {

using XReg = const Xbyak_aarch64::XReg;

jit_uni_brgemm_conv_comp_pad_kernel_t<isa>(
const jit_brgemm_conv_conf_t &ajcp);
jit_uni_brgemm_conv_comp_pad_kernel_t(const jit_brgemm_conv_conf_t &ajcp);

~jit_uni_brgemm_conv_comp_pad_kernel_t() = default;

Expand Down
15 changes: 11 additions & 4 deletions src/cpu/aarch64/jit_brgemm_post_ops.hpp
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*******************************************************************************
* Copyright 2020-2023 Intel Corporation
* Copyright 2024 FUJITSU LIMITED
* Copyright 2024 Arm Ltd. and affiliates
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -196,15 +197,18 @@ struct jit_brgemm_kernel_diff_bias_t : public jit_generator {
}

void generate() override {
size_t simd_w_;
size_t simd_w_ = 0;
switch (brg_.isa_impl) {
case sve_512:
simd_w_ = cpu_isa_traits<sve_512>::vlen / sizeof(float);
break;
case sve_256:
simd_w_ = cpu_isa_traits<sve_256>::vlen / sizeof(float);
break;
default: assert(!"unsupported isa");
default: {
assert(!"unsupported isa");
return;
}
}
preamble();
if (simd_w_ != cpu_sveLen / sizeof(float)) {
Expand Down Expand Up @@ -850,15 +854,18 @@ struct jit_brgemm_kernel_post_ops : public jit_generator {
}

void generate() override {
size_t simd_w_;
size_t simd_w_ = 0;
switch (brg.isa_impl) {
case sve_512:
simd_w_ = cpu_isa_traits<sve_512>::vlen / sizeof(float);
break;
case sve_256:
simd_w_ = cpu_isa_traits<sve_256>::vlen / sizeof(float);
break;
default: assert(!"unsupported isa");
default: {
assert(!"unsupported isa");
return;
}
}
preamble();
if (simd_w_ != cpu_sveLen / sizeof(float)) {
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/cpu_deconvolution_list.cpp
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
/*******************************************************************************
* Copyright 2019-2023 Intel Corporation
* Copyright 2022 FUJITSU LIMITED
* Copyright 2022 Arm Ltd. and affiliates
* Copyright 2022, 2024 Arm Ltd. and affiliates
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand All @@ -16,10 +16,9 @@
* limitations under the License.
*******************************************************************************/

#include "common/compiler_workarounds.hpp"
#include "cpu/cpu_engine.hpp"

#include "cpu/ref_deconvolution.hpp"

#if DNNL_X64
#include "cpu/x64/jit_avx512_core_amx_deconvolution.hpp"
#include "cpu/x64/jit_avx512_core_x8s8s32x_1x1_deconvolution.hpp"
Expand Down