Merge pull request #2414 from XavierAubert/cv32e40p/dev_dd_ww16_PR

CV32E40Pv2 Verification update Week 16 PR

cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv

@@ -20,6 +20,7 @@ class cv32e40p_instr extends riscv_instr;
   // additionnal helper fields
   bit is_post_incr;
   bit is_r_format ;
+  bit is_simd_imm_legal = 1;
 
   bit hw_loop_label;
 
@@ -676,7 +677,30 @@ class cv32e40p_instr extends riscv_instr;
     this.is_r_format       = rhs_.is_r_format;
   endfunction : do_copy
 
+  virtual function void override_imm();
+    if (category == SIMD) begin
+      if (is_simd_imm_legal) begin
+        case (instr_name) 
+          CV_EXTRACT_H, CV_EXTRACTU_H, CV_INSERT_H                    : imm[5:1] = 5'd0;
+          CV_EXTRACT_B, CV_EXTRACTU_B, CV_INSERT_B, CV_SHUFFLE_SCI_H  : imm[5:2] = 4'd0;
+          CV_SLL_SCI_B, CV_SRL_SCI_B, CV_SRA_SCI_B                    : imm[5:3] = 3'd0;
+          CV_SLL_SCI_H, CV_SRL_SCI_H, CV_SRA_SCI_H                    : imm[5:4] = 2'd0;
+        endcase
+      end
+      else begin
+        // below imms value lead to illegal exception
+        case (instr_name) 
+          CV_EXTRACT_H, CV_EXTRACTU_H, CV_INSERT_H                    : imm[5:1] = $urandom_range(1, 31);
+          CV_EXTRACT_B, CV_EXTRACTU_B, CV_INSERT_B, CV_SHUFFLE_SCI_H  : imm[5:2] = $urandom_range(1, 15);
+          CV_SLL_SCI_B, CV_SRL_SCI_B, CV_SRA_SCI_B                    : imm[5:3] = $urandom_range(1, 7);
+          CV_SLL_SCI_H, CV_SRL_SCI_H, CV_SRA_SCI_H                    : imm[5:4] = $urandom_range(1, 3);
+        endcase
+      end
+    end
+  endfunction : override_imm
+
   virtual function void update_imm_str();
+    override_imm();
     if (category == BRANCH_IMM) begin
       // for branch imm, immediate is split in two parts
       imm_str = $sformatf("%0d, %0d", $signed(imm[16:12]), $signed(imm[11:0]));

cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv

@@ -31,7 +31,6 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i
   int unsigned        loop_cnt           = 0;
   int unsigned        total_instr        = 0;
   int unsigned        loop_cnt_limit     = 0;
-  int unsigned        ignored_instr_cnt  = 0;
 
   `uvm_object_utils(cv32e40p_cv_instrs_multi_loops_streams)
   `uvm_object_new
@@ -47,14 +46,14 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i
     include_group   = new[1] ({RV32X});
     exclude_instr   = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW});
 
-    // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered)
-    ignored_instr_cnt = 4;
-    exclude_instr   = new[exclude_instr.size()+ignored_instr_cnt] ({exclude_instr, CV_MAX, CV_ADDN, CV_AVG_SCI_H, CV_SHUFFLEI3_SCI_B});
+    // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to be covered)
+      // example coding to reduce already covered instrs in previous accumulated coverage
+      // exclude_instr   = new[exclude_instr.size()+4] ({exclude_instr, CV_MAX, CV_ADDN, CV_AVG_SCI_H, CV_SHUFFLEI3_SCI_B});
     // these already covered in all cvg, can be ignored meantime - End
 
     if (include_load_store_base_sp) begin // cover c_[s|l]wsp insn only
       include_group   = new[include_group.size()+1] ({include_group, RV32C});
-      // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered)
+      // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to be covered)
       exclude_instr   = new[exclude_instr.size()+25] ({exclude_instr, C_LW, C_SW, C_ADDI4SPN, C_ADDI, C_LI, C_ADDI16SP, C_LUI,
         C_SRLI, C_SRAI, C_ANDI, C_SUB, C_XOR, C_OR, C_AND, C_BEQZ, C_BNEZ, C_SLLI, C_MV, C_EBREAK, C_ADD, C_NOP, C_J,
         C_JAL, C_JR, C_JALR});

cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv

@@ -74,7 +74,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;
 
   localparam MAX_HWLOOP_INSTR_GEN = 4095;
   rand riscv_reg_t      hwloop_avail_regs[];
-  rand bit[1:0]         num_loops_active;
+  rand int unsigned     num_loops_active;
   rand bit              gen_nested_loop; //nested or not-nested hwloop
   rand bit              use_setup_inst[2];
   rand bit              use_loop_counti_inst[2];
@@ -1324,6 +1324,49 @@ class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_h
   endfunction : new
 
 endclass : cv32e40p_xpulp_short_hwloop_stream_directed
+// directed test for more non-nested hwloop only with small loop count and lesser instrs
+class cv32e40p_xpulp_short_single_hwloop_stream_directed extends cv32e40p_xpulp_short_hwloop_stream;
+
+  `uvm_object_utils_begin(cv32e40p_xpulp_short_single_hwloop_stream_directed)
+      `uvm_field_int(num_loops_active, UVM_DEFAULT)
+      `uvm_field_int(gen_nested_loop, UVM_DEFAULT)
+      `uvm_field_sarray_int(use_setup_inst, UVM_DEFAULT)
+      `uvm_field_sarray_int(use_loop_counti_inst, UVM_DEFAULT)
+      `uvm_field_sarray_int(use_loop_starti_inst, UVM_DEFAULT)
+      `uvm_field_sarray_int(use_loop_endi_inst, UVM_DEFAULT)
+      `uvm_field_sarray_int(use_loop_setupi_inst, UVM_DEFAULT)
+      `uvm_field_sarray_int(hwloop_count, UVM_DEFAULT)
+      `uvm_field_sarray_int(hwloop_counti, UVM_DEFAULT)
+      `uvm_field_sarray_int(num_hwloop_instr, UVM_DEFAULT)
+      `uvm_field_sarray_int(num_hwloop_ctrl_instr, UVM_DEFAULT)
+      `uvm_field_sarray_int(num_fill_instr_loop_ctrl_to_loop_start, UVM_DEFAULT)
+      `uvm_field_int(num_fill_instr_in_loop1_till_loop0_setup, UVM_DEFAULT)
+      `uvm_field_int(setup_l0_before_l1_start, UVM_DEFAULT)
+      `uvm_field_sarray_int(num_instr_cv_start_to_loop_start_label, UVM_DEFAULT)
+      `uvm_field_int(loop0_high_count, UVM_DEFAULT)
+  `uvm_object_utils_end
+
+  constraint gen_hwloop_count_c {
+
+      solve gen_nested_loop, loop0_high_count before hwloop_count, hwloop_counti;
+      solve gen_nested_loop before loop0_high_count;
+
+      gen_nested_loop == 0;
+      num_loops_active inside {[800:1000]};
+
+      foreach(hwloop_counti[i]) {
+        hwloop_counti[i] inside {2,3};
+      }
+      foreach(hwloop_count[i]) {
+        hwloop_count[i]  inside {2,3};
+      }
+  }
+
+  function new(string name = "cv32e40p_xpulp_short_single_hwloop_stream_directed");
+      super.new(name);
+  endfunction : new
+
+endclass : cv32e40p_xpulp_short_single_hwloop_stream_directed
 
 
 //Class: cv32e40p_xpulp_long_hwloop_stream

cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml

@@ -62,3 +62,39 @@ tests:
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=debug_test_trigger
     num: 1
+
+  fpu_func_cov_improve_test:
+    build: uvmt_cv32e40p
+    description: directed custom test to improve missing coverage in cfg pulp_fpu
+    dir: cv32e40p/sim/uvmt
+    cmd: make test TEST=fpu_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000"
+    num: 1
+    skip_sim:
+      - pulp
+      - pulp_zfinx
+      - pulp_zfinx_1cyclat
+      - pulp_zfinx_2cyclat
+      - pulp_cluster
+      - pulp_cluster_fpu
+      - pulp_cluster_fpu_1cyclat
+      - pulp_cluster_fpu_2cyclat
+      - default
+      - no_pulp
+
+  zfinx_func_cov_improve_test:
+    build: uvmt_cv32e40p
+    description: directed custom test to improve missing coverage in cfg pulp_zfinx
+    dir: cv32e40p/sim/uvmt
+    cmd: make test TEST=zfinx_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000"
+    num: 1
+    skip_sim:
+      - pulp
+      - pulp_fpu
+      - pulp_fpu_1cyclat
+      - pulp_fpu_2cyclat
+      - pulp_cluster
+      - pulp_cluster_fpu
+      - pulp_cluster_fpu_1cyclat
+      - pulp_cluster_fpu_2cyclat
+      - default
+      - no_pulp

cv32e40p/regress/cv32e40pv2_fpu_instr.yaml

@@ -63,3 +63,39 @@ tests:
     dir: cv32e40p/sim/uvmt
     cmd: make test TEST=illegal_fp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000"
     num: 1
+
+  fpu_func_cov_improve_test:
+    build: uvmt_cv32e40p
+    description: directed custom test to improve missing coverage in cfg pulp_fpu
+    dir: cv32e40p/sim/uvmt
+    cmd: make test TEST=fpu_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000"
+    num: 1
+    skip_sim:
+      - pulp
+      - pulp_zfinx
+      - pulp_zfinx_1cyclat
+      - pulp_zfinx_2cyclat
+      - pulp_cluster
+      - pulp_cluster_fpu
+      - pulp_cluster_fpu_1cyclat
+      - pulp_cluster_fpu_2cyclat
+      - default
+      - no_pulp
+
+  zfinx_func_cov_improve_test:
+    build: uvmt_cv32e40p
+    description: directed custom test to improve missing coverage in cfg pulp_zfinx
+    dir: cv32e40p/sim/uvmt
+    cmd: make test TEST=zfinx_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000"
+    num: 1
+    skip_sim:
+      - pulp
+      - pulp_fpu
+      - pulp_fpu_1cyclat
+      - pulp_fpu_2cyclat
+      - pulp_cluster
+      - pulp_cluster_fpu
+      - pulp_cluster_fpu_1cyclat
+      - pulp_cluster_fpu_2cyclat
+      - default
+      - no_pulp