DSim-compatible updates for CV32E20

[MikeOpenHWGroup]

This is a companion PR to openhwgroup/cv32e20-dv#3.

[MikeOpenHWGroup]

Hi @zchamski and @AyoubJalali, I am hoping that you can both spare some time to review this PR. These are changes that should not affect CVA6, but I want to be double-sure before merging.

Below is summary of the changes:

• .gitignore : a little clean-up. Does not affect functionality of any env using core-v-verif.
• LICENSE.md : a little clean-up. Does not affect functionality of any env using core-v-verif.
• lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv : define is_active as a uvm_active_passive_enum, instead of a bit. This was a latent bug that VCS doesn't care about, but DSim (correctly) throws a compiel error.
• lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_base_seq.sv : delete whitespace, update comments and add one additional call to uvm_info. No impact on functionality.
• lib/uvm_components/uvmc_rvfi_reference_model/uvmc_rvfi_spike.sv : Change of functionality! Only call Spike tasks if USE_ISS is set.
• lib/uvm_components/uvmc_rvfi_scoreboard/uvmc_rvfi_scoreboard.sv : Change of functionality! Only call Spike tasks if USE_ISS is set.
• lib/uvm_components/uvmc_rvfi_scoreboard/uvmc_rvfi_scoreboard_utils.sv : add a TODO comment. No change in functionality.
• mk/Common.mk : add banner to target svlib. Add new vars and targets rvvi_stub. No change in functionality.
• mk/uvmt/dsim.mk : Significant updates. Only affects users of DSim.
• mk/uvmt/uvmt.mk : Add new vars and new target to display vars. No change in functionality.
• vendor_lib/.gitignore : Fix to prevent svlib.so from Verilab being checked in (should be generated).

[AyoubJalali]

LGTM !

[zchamski]

Aside from a typo in variable name LGTM. RTL cleanup is a separate story (and should be a separate task).

[zchamski]

LGTM!

[JeanRochCoulon]

For info, I am trying CVA6 with this PR. I let you know.

[JeanRochCoulon]

When using this PR in CVA6 project, I get this error message: