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Use target independent builtins #104

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merged 2 commits into from
Feb 2, 2024
Merged

Use target independent builtins #104

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ae287d9
This patch replaces __builtin_riscv_cv_bitmanip_ror with target indep…
adeel10x Jan 17, 2024
9024d06
Used PatGprGpr class to define instruction selection pattern for cv.r…
adeel10x Jan 17, 2024
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1 change: 0 additions & 1 deletion clang/include/clang/Basic/BuiltinsRISCVCOREV.def
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Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,6 @@ TARGET_BUILTIN(bitmanip_ff1, "UZcUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_fl1, "UZcUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_clb, "UZcUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_cnt, "UZcUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_ror, "UZiUZiUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_bitrev, "UZiUZiIUcIUc", "nc", "xcvbitmanip")

TARGET_BUILTIN(mac_mac, "UZiUZiUZiUZi", "nc", "xcvmac")
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2 changes: 1 addition & 1 deletion clang/lib/Headers/riscv_corev_bitmanip.h
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Expand Up @@ -58,7 +58,7 @@ static __inline__ uint8_t __DEFAULT_FN_ATTRS __riscv_cv_bitmanip_cnt(unsigned lo
}

static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_bitmanip_ror(unsigned long a, unsigned long b) {
return __builtin_riscv_cv_bitmanip_ror(a, b);
return __builtin_rotateright32(a, b);
}

#define __riscv_cv_bitmanip_bitrev(rs1, PTS, RADIX) \
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip-c-api.c
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Expand Up @@ -90,7 +90,7 @@ uint32_t test_cnt(uint32_t a) {
}

// CHECK-LABEL: @test_ror
// CHECK: @llvm.riscv.cv.bitmanip.ror
// CHECK: @llvm.fshr.i32
uint32_t test_ror(uint32_t a, uint32_t b) {
return __riscv_cv_bitmanip_ror(a, b);
}
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15 changes: 0 additions & 15 deletions clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip.c
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Expand Up @@ -199,21 +199,6 @@ uint32_t test_cnt(uint32_t a) {
return __builtin_riscv_cv_bitmanip_cnt(a);
}

// CHECK-LABEL: @test_ror(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.bitmanip.ror(i32 [[TMP0]], i32 [[TMP1]])
// CHECK-NEXT: ret i32 [[TMP2]]
//
uint32_t test_ror(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_bitmanip_ror(a, b);
}

// CHECK-LABEL: @test_bitrev(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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2 changes: 0 additions & 2 deletions llvm/include/llvm/IR/IntrinsicsRISCV.td
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Expand Up @@ -1730,8 +1730,6 @@ def int_riscv_cv_bitmanip_fl1 : ScalarCoreVBitManipGprIntrinsic;
def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic;
def int_riscv_cv_bitmanip_cnt : ScalarCoreVBitManipGprIntrinsic;

def int_riscv_cv_bitmanip_ror : ScalarCoreVBitManipGprGprIntrinsic;

def int_riscv_cv_bitmanip_bitrev
: Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
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14 changes: 8 additions & 6 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -272,13 +272,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT,
Custom);

if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
if (Subtarget.is64Bit())
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
} else {
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);

if (!Subtarget.hasExtXcvbitmanip()) {
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@adeel10x adeel10x Jan 17, 2024 •
edited
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@PaoloS02 This is something you might want to have a look at.
I have edited this code because RISCV Base ISA doesn't have a rotate right instruction and thus during legalization, it expands the ROTR operation into a combination of other supported operations (srl, neg, sll ,or).

if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
if (Subtarget.is64Bit())
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
} else {
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
}
}

// With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
// pattern match it directly in isel.
setOperationAction(ISD::BSWAP, XLenVT,
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
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Expand Up @@ -1222,8 +1222,8 @@ let Predicates = [HasExtXcvbitmanip, IsRV32] in {
def : PatGpr<int_riscv_cv_bitmanip_clb, CV_CLB>;
def : PatGpr<int_riscv_cv_bitmanip_cnt, CV_CNT>;

def : PatGprGpr<int_riscv_cv_bitmanip_ror, CV_ROR>;

def : PatGprGpr<rotr, CV_ROR>;
def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts, cv_tuimm2:$radix),
(CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
}
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/corev/bitmanip.ll
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Expand Up @@ -155,14 +155,14 @@ define i32 @test.cv.cnt(i32 %a) {
ret i32 %1
}

declare i32 @llvm.riscv.cv.bitmanip.ror(i32, i32)
declare i32 @llvm.fshr.i32(i32, i32, i32)

define i32 @test.cv.ror(i32 %a, i32 %b) {
; CHECK-LABEL: test.cv.ror:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.ror a0, a0, a1
; CHECK-NEXT: ret
%1 = call i32 @llvm.riscv.cv.bitmanip.ror(i32 %a, i32 %b)
%1 = call i32 @llvm.fshr.i32(i32 %a, i32 %a , i32 %b)
ret i32 %1
}

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