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Merge pull request #898 from pascalgouedo/dev_dd_pgo_doc
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Slight User Manual corrections
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@davideschiavone
davideschiavone authored Nov 7, 2023
2 parents 688a28a + b13c97e commit 40f6edf
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Showing 2 changed files with 17 additions and 9 deletions.
24 changes: 16 additions & 8 deletions docs/source/control_status_registers.rst
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Expand Up @@ -445,7 +445,7 @@ Detailed:
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 30:15 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 14:13 | RW | **FS:** Floating point State |
| 14:13 | RW | **FS:** Floating point State (See note below) |
| | | |
| | | 00 = Off |
| | | |
Expand All @@ -457,13 +457,13 @@ Detailed:
| | | |
| | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 12:11 | RO | **MPP:** Machine Previous Priviledge mode |
| 12:11 | RW | **MPP:** Machine Previous Priviledge mode |
| | | |
| | | 11 when the user mode is not enabled. |
| | | Hardwired to 11 when the User mode is not enabled. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 10:8 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 7 | RO | **MPIE:** Machine Previous Interrupt Enable |
| 7 | RW | **MPIE:** Machine Previous Interrupt Enable |
| | | |
| | | When an exception is encountered, MPIE will be set to MIE. |
| | | When the mret instruction is executed, the value of MPIE will be stored to MIE. |
Expand All @@ -478,6 +478,10 @@ Detailed:
| 2:0 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+

.. note::

As allowed by RISC-V ISA and to simplify MSTATUS.FS update in the design, the state is updated to Dirty when executing any F instructions except for all FSW ones.

.. only:: USER

User Status (``ustatus``)
Expand Down Expand Up @@ -652,8 +656,10 @@ Detailed:
| 4:0 | RW | **Exception Code** (See note below) |
+-------------+-----------+----------------------------------------------------------------------------------+

**NOTE**: software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
.. note::

Software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.


Machine Trap Value (``mtval``)
Expand Down Expand Up @@ -1603,8 +1609,10 @@ Detailed:
| 4:0 | RW | **Exception Code** (See note below) |
+-------------+-----------+------------------------------------------------------------------------------------+

**NOTE**: software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
.. note::

Software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.


.. only:: PMP
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2 changes: 1 addition & 1 deletion docs/source/fpu.rst
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Expand Up @@ -25,7 +25,7 @@ precision can be enabled by setting the parameter **FPU** of the ``cv32e40p_top`
to 1. This will extend the CV32E40P decoder accordingly and will instantiate the FPU.
The FPU repository used by the CV32E40P is available at `https://github.com/openhwgroup/cvfpu <https://github.com/openhwgroup/cvfpu/tree/3116391bf66660f806b45e212b9949c528b4e270>`_ and
its documentation can be found `here <https://github.com/openhwgroup/cvfpu/blob/3116391bf66660f806b45e212b9949c528b4e270/docs/README.md>`_.
CVFPU v1.0.0 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository.
CVFPU v0.8.1 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository.

cv32e40p_fpu_manifest file is listing all necessary files for both the Core and CVFPU.

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