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Merge pull request #875 from openhwgroup/dev
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Automatic PR dev->master
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@davideschiavone
davideschiavone authored Sep 19, 2023
2 parents c904868 + c520546 commit 57aacac
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Showing 2 changed files with 24 additions and 7 deletions.
27 changes: 20 additions & 7 deletions bhv/cv32e40p_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1351,12 +1351,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
end
if (trace_wb.m_valid && !s_skip_wb) begin
if (r_pipe_freeze_trace.rf_we_wb) begin
if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0])) begin
trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0]) && trace_wb.m_mem_req_id_valid[0]) begin
trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1])) begin
trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
trace_wb.m_mem_req_id_valid[0] = 1'b0;
end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1]) && trace_wb.m_mem_req_id_valid[1]) begin
trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
trace_wb.m_mem_req_id_valid[1] = 1'b0;
end
end

Expand Down Expand Up @@ -1395,14 +1397,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;

if (r_pipe_freeze_trace.regfile_we_lsu) begin
->e_dev_commit_rf_to_ex_4;
if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg)) begin
if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin
trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
trace_ex.m_got_first_data = 1'b1;
end else if (cnt_data_resp == trace_ex.m_mem_req_id[1]) begin
trace_ex.m_mem_req_id_valid[0] = 1'b0;
end else if ((cnt_data_resp == trace_ex.m_mem_req_id[1]) && trace_ex.m_mem_req_id_valid[1]) begin
trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
trace_ex.m_got_first_data = 1'b1;
trace_ex.m_mem_req_id_valid[1] = 1'b0;
end
end

Expand Down Expand Up @@ -1543,6 +1547,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
cnt_data_req = cnt_data_req + 1;
trace_id.m_is_memory = 1'b1;
trace_id.m_mem_req_id[0] = cnt_data_req;
trace_id.m_mem_req_id_valid[0] = 1'b1;

trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
if (r_pipe_freeze_trace.data_misaligned) begin
Expand All @@ -1555,13 +1560,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_id.m_data_missaligned = 1'b1;
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = cnt_data_req;
trace_id.m_mem_req_id_valid[1] = 1'b1;
end
end else begin
trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1;
end
if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = 0;
trace_id.m_mem_req_id_valid[1] = 1'b1;
trace_id.m_mem_req_id_valid[0] = 1'b0;
end
end
hwloop_to_id();
Expand All @@ -1580,6 +1588,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
if (trace_id.m_mem_req_id[0] != 0) begin
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = 0;
trace_id.m_mem_req_id_valid[0] = 1'b0;
trace_id.m_mem_req_id_valid[1] = 1'b1;
end
end
end //trace_if.m_valid
Expand Down Expand Up @@ -1609,7 +1619,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
cnt_data_req = cnt_data_req + 1;
trace_id.m_is_memory = 1'b1;
trace_id.m_mem_req_id[0] = cnt_data_req;

trace_id.m_mem_req_id_valid[0] = 1'b1;
trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
if (r_pipe_freeze_trace.data_misaligned) begin
cnt_data_req = cnt_data_req + 1;
Expand All @@ -1620,11 +1630,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_id.m_data_missaligned = 1'b1;
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = cnt_data_req;
trace_id.m_mem_req_id_valid[1] = 1'b1;
end
end
if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = 0;
trace_id.m_mem_req_id_valid[0] = 1'b0;
trace_id.m_mem_req_id_valid[1] = 1'b1;
end
end else if (r_pipe_freeze_trace.rf_we_wb && !r_pipe_freeze_trace.ex_reg_we) begin
trace_id.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
Expand Down
4 changes: 4 additions & 0 deletions bhv/insn_trace.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@
logic m_is_apu_ok;
integer m_apu_req_id;
integer m_mem_req_id[1:0];
logic [ 1:0] m_mem_req_id_valid;
logic m_data_missaligned;
logic m_got_first_data;
logic m_got_ex_reg;
Expand Down Expand Up @@ -150,6 +151,7 @@
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_trap = 1'b0;
this.m_fflags_we_non_apu = 1'b0;
this.m_frm_we_non_apu = 1'b0;
Expand Down Expand Up @@ -208,6 +210,7 @@
this.m_apu_req_id = 0;
this.m_mem_req_id[0] = 0;
this.m_mem_req_id[1] = 0;
this.m_mem_req_id_valid = '0;
this.m_data_missaligned = 1'b0;
this.m_got_first_data = 1'b0;
this.m_got_ex_reg = 1'b0;
Expand Down Expand Up @@ -272,6 +275,7 @@
this.m_is_apu_ok = m_source.m_is_apu_ok;
this.m_apu_req_id = m_source.m_apu_req_id;
this.m_mem_req_id = m_source.m_mem_req_id;
this.m_mem_req_id_valid = m_source.m_mem_req_id_valid;
this.m_data_missaligned = m_source.m_data_missaligned;
this.m_got_first_data = m_source.m_got_first_data;
this.m_got_ex_reg = m_source.m_got_ex_reg;
Expand Down

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