Merge pull request #855 from pascalgouedo/dev_dd_pgo_rtl

HW loop alignement to User Manual
openhwgroup · Aug 22, 2023 · 6fb6ada · 6fb6ada
2 parents be1e881 + 770d87c
commit 6fb6ada
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Showing 3 changed files with 9 additions and 22 deletions.
diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv
@@ -78,7 +78,6 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
   // HWLoop signls
   input  logic [31:0]       pc_id_i,
-  input  logic              is_compressed_i,
 
   // from hwloop_regs
   input  logic [1:0] [31:0] hwlp_start_addr_i,
@@ -208,13 +207,13 @@ module cv32e40p_controller import cv32e40p_pkg::*;
   // Debug state
   debug_state_e debug_fsm_cs, debug_fsm_ns;
 
-  logic jump_done, jump_done_q, jump_in_dec, branch_in_id_dec, branch_in_id;
+  logic jump_done, jump_done_q, jump_in_dec, branch_in_id;
 
   logic data_err_q;
 
   logic debug_mode_q, debug_mode_n;
   logic ebrk_force_debug_mode;
-  logic is_hwlp_illegal, is_hwlp_body;
+  logic is_hwlp_body;
   logic illegal_insn_q, illegal_insn_n;
   logic debug_req_entry_q, debug_req_entry_n;
   logic debug_force_wakeup_q, debug_force_wakeup_n;
@@ -292,7 +291,6 @@ module cv32e40p_controller import cv32e40p_pkg::*;
     jump_in_dec            = ctrl_transfer_insn_in_dec_i == BRANCH_JALR || ctrl_transfer_insn_in_dec_i == BRANCH_JAL;
 
     branch_in_id           = ctrl_transfer_insn_in_id_i == BRANCH_COND;
-    branch_in_id_dec       = ctrl_transfer_insn_in_dec_i == BRANCH_COND;
 
     ebrk_force_debug_mode  = (debug_ebreakm_i && current_priv_lvl_i == PRIV_LVL_M) ||
                              (debug_ebreaku_i && current_priv_lvl_i == PRIV_LVL_U);
@@ -317,8 +315,6 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
     hwlp_mask_o             = 1'b0;
 
-    is_hwlp_illegal         = 1'b0;
-
     hwlp_dec_cnt_o          = '0;
     hwlp_end_4_id_d         = 1'b0;
 
@@ -527,9 +523,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
             else
               begin
 
-                is_hwlp_illegal  = is_hwlp_body & (jump_in_dec || branch_in_id_dec || mret_insn_i || uret_insn_i || dret_insn_i || is_compressed_i || fencei_insn_i || wfi_active);
-
-                if(illegal_insn_i || is_hwlp_illegal) begin
+                if (illegal_insn_i) begin
 
                   halt_if_o         = 1'b1;
                   halt_id_o         = 1'b0;
@@ -752,9 +746,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
             else
               begin
 
-                is_hwlp_illegal  = (jump_in_dec || branch_in_id_dec || mret_insn_i || uret_insn_i || dret_insn_i || is_compressed_i || fencei_insn_i || wfi_active);
-
-                if(illegal_insn_i || is_hwlp_illegal) begin
+                if (illegal_insn_i) begin
 
                   halt_if_o         = 1'b1;
                   halt_id_o         = 1'b1;
@@ -785,12 +777,6 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
                     end
 
-                    ecall_insn_i: begin
-                      halt_if_o     = 1'b1;
-                      halt_id_o     = 1'b1;
-                      ctrl_fsm_ns   = FLUSH_EX;
-                    end
-
                     csr_status_i: begin
                       halt_if_o     = 1'b1;
                       ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
@@ -1565,7 +1551,7 @@ endgenerate
 
     property p_no_hwlp;
        @(posedge clk) (1'b1) |-> ((pc_mux_o != PC_HWLOOP) && (ctrl_fsm_cs != DECODE_HWLOOP) &&
-                                  (hwlp_mask_o == 1'b0) && (is_hwlp_illegal == 'b0) && (is_hwlp_body == 'b0) &&
+                                  (hwlp_mask_o == 1'b0) && (is_hwlp_body == 'b0) &&
                                   (hwlp_start_addr_i == 'b0) && (hwlp_end_addr_i == 'b0) && (hwlp_counter_i[1] == 32'b0) && (hwlp_counter_i[0] == 32'b0) &&
                                   (hwlp_dec_cnt_o == 2'b0) && (hwlp_jump_o == 1'b0) && (hwlp_targ_addr_o == 32'b0) &&
                                   (hwlp_end0_eq_pc == 1'b0) && (hwlp_end1_eq_pc == 1'b0) && (hwlp_counter0_gt_1 == 1'b0) && (hwlp_counter1_gt_1 == 1'b0) &&

diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv
@@ -1136,8 +1136,7 @@ module cv32e40p_id_stage
       .trap_addr_mux_o(trap_addr_mux_o),
 
       // HWLoop signls
-      .pc_id_i        (pc_id_i),
-      .is_compressed_i(is_compressed_i),
+      .pc_id_i(pc_id_i),
 
       .hwlp_start_addr_i(hwlp_start_o),
       .hwlp_end_addr_i  (hwlp_end_o),

diff --git a/util/format-verible b/util/format-verible
@@ -11,4 +11,6 @@ then
 find rtl/ bhv/ -not -path "*rtl/vendor*" \
     -name '*.sv' | \
     xargs verible-verilog-format --inplace 2> /dev/zero
-fi
+else
+echo "verible-verilog-format not available!"
+fi