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Merge pull request #861 from YoannPruvost/dev_rvfi_gpr_when_apu
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Rvfi - Fixing gpr reporting when apu collide with instruction in EX
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davideschiavone authored Sep 5, 2023
2 parents 310f163 + 5ee93bf commit 8c5bcde
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Showing 3 changed files with 23 additions and 11 deletions.
30 changes: 20 additions & 10 deletions bhv/cv32e40p_rvfi.sv
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,7 @@ module cv32e40p_rvfi
input logic apu_multicycle_i,
input logic wb_contention_lsu_i,
input logic wb_contention_i,
input logic regfile_we_lsu_i,

input logic branch_in_ex_i,
input logic branch_decision_ex_i,
Expand Down Expand Up @@ -1072,7 +1073,12 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;

//those event are for debug purpose
event e_dev_send_wb_1, e_dev_send_wb_2;
event e_dev_commit_rf_to_ex_1, e_dev_commit_rf_to_ex_2, e_dev_commit_rf_to_ex_3;
event
e_dev_commit_rf_to_ex_1,
e_dev_commit_rf_to_ex_2,
e_dev_commit_rf_to_ex_3,
e_dev_commit_rf_to_ex_4,
e_dev_commit_rf_to_ex_5;
event e_if_2_id_1, e_if_2_id_2;
event e_ex_to_wb_1, e_ex_to_wb_2;
event e_id_to_ex_1, e_id_to_ex_2;
Expand All @@ -1083,7 +1089,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
e_send_rvfi_trace_ex_1,
e_send_rvfi_trace_ex_2,
e_send_rvfi_trace_ex_3,
e_send_rvfi_trace_ex_4;
e_send_rvfi_trace_ex_4,
e_send_rvfi_trace_ex_5,
e_send_rvfi_trace_ex_6;
event e_send_rvfi_trace_wb_1, e_send_rvfi_trace_wb_2, e_send_rvfi_trace_wb_3;
event e_send_rvfi_trace_id_1;

Expand Down Expand Up @@ -1391,8 +1399,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
`CSR_FROM_PIPE(ex, tdata2)
tinfo_to_ex();

if (r_pipe_freeze_trace.rf_we_wb) begin
if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_id.m_got_ex_reg)) begin
if (r_pipe_freeze_trace.regfile_we_lsu) begin
->e_dev_commit_rf_to_ex_4;
if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg)) begin
trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
trace_ex.m_got_first_data = 1'b1;
Expand All @@ -1409,7 +1418,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_ex.m_valid = 1'b0;
->e_send_rvfi_trace_ex_2;
end else begin
if (r_pipe_freeze_trace.rf_we_wb) begin
if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin
->e_dev_commit_rf_to_ex_1;
if (trace_ex.m_got_ex_reg) begin
trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
Expand All @@ -1434,10 +1443,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
minstret_to_ex();
end
send_rvfi(trace_ex);
->e_send_rvfi_trace_ex_6;
end
trace_ex.m_valid = 1'b0;
end
end else if (r_pipe_freeze_trace.rf_we_wb && !s_was_flush) begin
end else if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port && !s_was_flush) begin
->e_dev_commit_rf_to_ex_2;
if (trace_ex.m_got_ex_reg) begin
trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
Expand All @@ -1452,7 +1462,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
end
end

s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
//EX_STAGE
if (trace_id.m_valid) begin
mtvec_to_id();
Expand Down Expand Up @@ -1516,7 +1526,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_ex.m_valid = 1'b0;
->e_send_rvfi_trace_ex_3;
end
if (r_pipe_freeze_trace.ex_reg_we && !r_pipe_freeze_trace.apu_rvalid) begin
if (r_pipe_freeze_trace.ex_reg_we && !s_apu_to_alu_port) begin
trace_id.m_ex_fw = 1'b1;
trace_id.m_rd_addr[0] = r_pipe_freeze_trace.ex_reg_addr;
trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.ex_reg_wdata;
Expand Down Expand Up @@ -1548,7 +1558,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_id.m_mem_req_id[0] = 0;
end
end
->e_id_to_ex_1;
hwloop_to_id();
trace_ex.move_down_pipe(trace_id); // The instruction moves forward from ID to EX
trace_id.m_valid = 1'b0;
Expand All @@ -1567,7 +1576,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_id.m_mem_req_id[0] = 0;
end
end
end
end //trace_if.m_valid

//ID_STAGE
if (s_new_valid_insn) begin // There is a new valid instruction
Expand All @@ -1585,6 +1594,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
trace_wb.move_down_pipe(trace_ex);
end else begin
send_rvfi(trace_ex);
->e_send_rvfi_trace_ex_5;
end
end
trace_ex.m_valid = 1'b0;
Expand Down
2 changes: 1 addition & 1 deletion bhv/cv32e40p_tb_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,7 @@ module cv32e40p_tb_wrapper
.apu_multicycle_i (cv32e40p_top_i.core_i.ex_stage_i.apu_multicycle),
.wb_contention_lsu_i(cv32e40p_top_i.core_i.ex_stage_i.wb_contention_lsu),
.wb_contention_i (cv32e40p_top_i.core_i.ex_stage_i.wb_contention),

.regfile_we_lsu_i (cv32e40p_top_i.core_i.ex_stage_i.regfile_we_lsu),
// .rf_we_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_we_fw_i),
// .rf_addr_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
// .rf_wdata_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),
Expand Down
2 changes: 2 additions & 0 deletions bhv/pipe_freeze_trace.sv
Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,7 @@ typedef struct {
logic apu_multicycle;
logic wb_contention_lsu;
logic wb_contention;
logic regfile_we_lsu;

logic branch_in_ex;
logic branch_decision_ex;
Expand Down Expand Up @@ -437,6 +438,7 @@ task monitor_pipeline();
r_pipe_freeze_trace.apu_multicycle = apu_multicycle_i;
r_pipe_freeze_trace.wb_contention_lsu = wb_contention_lsu_i;
r_pipe_freeze_trace.wb_contention = wb_contention_i;
r_pipe_freeze_trace.regfile_we_lsu = regfile_we_lsu_i;

r_pipe_freeze_trace.branch_in_ex = branch_in_ex_i;
r_pipe_freeze_trace.branch_decision_ex = branch_decision_ex_i;
Expand Down

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