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Merge pull request #715 from openhwgroup/dev
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@davideschiavone
davideschiavone authored Jun 27, 2022
2 parents 52113dc + 81b522e commit d0d1c25
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39 changes: 39 additions & 0 deletions .github/workflows/lint.yml
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@@ -0,0 +1,39 @@
# Copyright 2022 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

# Run all lint checks
name: lint
on: [push, pull_request]

env:
VERIBLE_VERSION: 0.0-1149-g7eae750

jobs:
##################
# Verible Fromat #
##################
format_verilog:
name: Format Verilog Sources
# This job runs on Linux (fixed ubuntu version)
runs-on: ubuntu-18.04
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
with:
python-version: 3.9
- name: Install requirements
run: pip install -r python-requirements.txt
- name: Install Verible
run: |
set -e
mkdir -p build/verible
cd build/verible
curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/v$VERIBLE_VERSION/verible-v$VERIBLE_VERSION-Ubuntu-18.04-bionic-x86_64.tar.gz
sudo mkdir -p /tools/verible && sudo chmod 777 /tools/verible
tar -C /tools/verible -xf verible.tar.gz --strip-components=1
echo "PATH=$PATH:/tools/verible/bin" >> $GITHUB_ENV
- name: Run Format
run: |
util/format-verible
util/git-diff.py --error-msg "::error ::Found differences, run util/format-verible before committing."
1 change: 1 addition & 0 deletions README.md
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Expand Up @@ -65,6 +65,7 @@ To get started, please check out the ["Good First Issue"
list](https://github.com/openhwgroup/cv32e40p/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).

The RTL code has been formatted with ["Verible"](https://github.com/google/verible) v0.0-1149-g7eae750.
Run `./util/format-verible` to format all the files.

## Issues and Troubleshooting

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237 changes: 118 additions & 119 deletions bhv/cv32e40p_tb_wrapper.sv
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Expand Up @@ -25,12 +25,11 @@
`include "cv32e40p_tracer.sv"
`endif

module cv32e40p_tb_wrapper
#(
module cv32e40p_tb_wrapper #(
parameter PULP_XPULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
parameter PULP_CLUSTER = 0, // PULP Cluster interface (incl. p.elw)
parameter FPU = 0, // Floating Point Unit (interfaced via APU interface)
parameter PULP_ZFINX = 0, // Float-in-General Purpose registers
parameter PULP_CLUSTER = 0, // PULP Cluster interface (incl. p.elw)
parameter FPU = 0, // Floating Point Unit (interfaced via APU interface)
parameter PULP_ZFINX = 0, // Float-in-General Purpose registers
parameter NUM_MHPMCOUNTERS = 1
) (
// Clock and Reset
Expand Down Expand Up @@ -79,7 +78,7 @@ module cv32e40p_tb_wrapper
input logic fetch_enable_i,
output logic core_sleep_o
);

`ifdef CV32E40P_ASSERT_ON

// RTL Assertions
Expand All @@ -103,93 +102,93 @@ module cv32e40p_tb_wrapper
.PULP_ZFINX (PULP_ZFINX),
.NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
) core_log_i (
.clk_i (cv32e40p_wrapper_i.core_i.id_stage_i.clk),
.is_decoding_i (cv32e40p_wrapper_i.core_i.id_stage_i.is_decoding_o),
.illegal_insn_dec_i (cv32e40p_wrapper_i.core_i.id_stage_i.illegal_insn_dec),
.hart_id_i (cv32e40p_wrapper_i.core_i.hart_id_i),
.pc_id_i (cv32e40p_wrapper_i.core_i.pc_id)
.clk_i (cv32e40p_wrapper_i.core_i.id_stage_i.clk),
.is_decoding_i (cv32e40p_wrapper_i.core_i.id_stage_i.is_decoding_o),
.illegal_insn_dec_i(cv32e40p_wrapper_i.core_i.id_stage_i.illegal_insn_dec),
.hart_id_i (cv32e40p_wrapper_i.core_i.hart_id_i),
.pc_id_i (cv32e40p_wrapper_i.core_i.pc_id)
);
`endif // SYNTHESIS

`ifdef CV32E40P_APU_TRACE
cv32e40p_apu_tracer apu_tracer_i (
.clk_i (cv32e40p_wrapper_i.core_i.rst_ni),
.rst_n (cv32e40p_wrapper_i.core_i.clk_i),
.hart_id_i (cv32e40p_wrapper_i.core_i.hart_id_i),
.apu_valid_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_valid),
.apu_waddr_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_waddr),
.apu_result_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_result)
.clk_i (cv32e40p_wrapper_i.core_i.rst_ni),
.rst_n (cv32e40p_wrapper_i.core_i.clk_i),
.hart_id_i (cv32e40p_wrapper_i.core_i.hart_id_i),
.apu_valid_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_valid),
.apu_waddr_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_waddr),
.apu_result_i(cv32e40p_wrapper_i.core_i.ex_stage_i.apu_result)
);
`endif

`ifdef CV32E40P_TRACE_EXECUTION
cv32e40p_tracer #(
.FPU (FPU),
.PULP_ZFINX (PULP_ZFINX)
) tracer_i (
.clk_i (cv32e40p_wrapper_i.core_i.clk_i), // always-running clock for tracing
.rst_n (cv32e40p_wrapper_i.core_i.rst_ni),

.hart_id_i (cv32e40p_wrapper_i.core_i.hart_id_i),

.pc (cv32e40p_wrapper_i.core_i.id_stage_i.pc_id_i),
.instr (cv32e40p_wrapper_i.core_i.id_stage_i.instr),
.controller_state_i (cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
.compressed (cv32e40p_wrapper_i.core_i.id_stage_i.is_compressed_i),
.id_valid (cv32e40p_wrapper_i.core_i.id_stage_i.id_valid_o),
.is_decoding (cv32e40p_wrapper_i.core_i.id_stage_i.is_decoding_o),
.is_illegal (cv32e40p_wrapper_i.core_i.id_stage_i.illegal_insn_dec),
.trigger_match (cv32e40p_wrapper_i.core_i.id_stage_i.trigger_match_i),
.rs1_value (cv32e40p_wrapper_i.core_i.id_stage_i.operand_a_fw_id),
.rs2_value (cv32e40p_wrapper_i.core_i.id_stage_i.operand_b_fw_id),
.rs3_value (cv32e40p_wrapper_i.core_i.id_stage_i.alu_operand_c),
.rs2_value_vec (cv32e40p_wrapper_i.core_i.id_stage_i.alu_operand_b),

.rs1_is_fp (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_a),
.rs2_is_fp (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_b),
.rs3_is_fp (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_c),
.rd_is_fp (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_d),

.ex_valid (cv32e40p_wrapper_i.core_i.ex_valid),
.ex_reg_addr (cv32e40p_wrapper_i.core_i.regfile_alu_waddr_fw),
.ex_reg_we (cv32e40p_wrapper_i.core_i.regfile_alu_we_fw),
.ex_reg_wdata (cv32e40p_wrapper_i.core_i.regfile_alu_wdata_fw),

.ex_data_addr (cv32e40p_wrapper_i.core_i.data_addr_o),
.ex_data_req (cv32e40p_wrapper_i.core_i.data_req_o),
.ex_data_gnt (cv32e40p_wrapper_i.core_i.data_gnt_i),
.ex_data_we (cv32e40p_wrapper_i.core_i.data_we_o),
.ex_data_wdata (cv32e40p_wrapper_i.core_i.data_wdata_o),
.data_misaligned (cv32e40p_wrapper_i.core_i.data_misaligned),

.ebrk_insn (cv32e40p_wrapper_i.core_i.id_stage_i.ebrk_insn_dec),
.debug_mode (cv32e40p_wrapper_i.core_i.debug_mode),
.FPU (FPU),
.PULP_ZFINX(PULP_ZFINX)
) tracer_i (
.clk_i(cv32e40p_wrapper_i.core_i.clk_i), // always-running clock for tracing
.rst_n(cv32e40p_wrapper_i.core_i.rst_ni),

.hart_id_i(cv32e40p_wrapper_i.core_i.hart_id_i),

.pc (cv32e40p_wrapper_i.core_i.id_stage_i.pc_id_i),
.instr (cv32e40p_wrapper_i.core_i.id_stage_i.instr),
.controller_state_i(cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
.compressed (cv32e40p_wrapper_i.core_i.id_stage_i.is_compressed_i),
.id_valid (cv32e40p_wrapper_i.core_i.id_stage_i.id_valid_o),
.is_decoding (cv32e40p_wrapper_i.core_i.id_stage_i.is_decoding_o),
.is_illegal (cv32e40p_wrapper_i.core_i.id_stage_i.illegal_insn_dec),
.trigger_match (cv32e40p_wrapper_i.core_i.id_stage_i.trigger_match_i),
.rs1_value (cv32e40p_wrapper_i.core_i.id_stage_i.operand_a_fw_id),
.rs2_value (cv32e40p_wrapper_i.core_i.id_stage_i.operand_b_fw_id),
.rs3_value (cv32e40p_wrapper_i.core_i.id_stage_i.alu_operand_c),
.rs2_value_vec (cv32e40p_wrapper_i.core_i.id_stage_i.alu_operand_b),

.rs1_is_fp(cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_a),
.rs2_is_fp(cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_b),
.rs3_is_fp(cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_c),
.rd_is_fp (cv32e40p_wrapper_i.core_i.id_stage_i.regfile_fp_d),

.ex_valid (cv32e40p_wrapper_i.core_i.ex_valid),
.ex_reg_addr (cv32e40p_wrapper_i.core_i.regfile_alu_waddr_fw),
.ex_reg_we (cv32e40p_wrapper_i.core_i.regfile_alu_we_fw),
.ex_reg_wdata(cv32e40p_wrapper_i.core_i.regfile_alu_wdata_fw),

.ex_data_addr (cv32e40p_wrapper_i.core_i.data_addr_o),
.ex_data_req (cv32e40p_wrapper_i.core_i.data_req_o),
.ex_data_gnt (cv32e40p_wrapper_i.core_i.data_gnt_i),
.ex_data_we (cv32e40p_wrapper_i.core_i.data_we_o),
.ex_data_wdata (cv32e40p_wrapper_i.core_i.data_wdata_o),
.data_misaligned(cv32e40p_wrapper_i.core_i.data_misaligned),

.ebrk_insn(cv32e40p_wrapper_i.core_i.id_stage_i.ebrk_insn_dec),
.debug_mode(cv32e40p_wrapper_i.core_i.debug_mode),
.ebrk_force_debug_mode (cv32e40p_wrapper_i.core_i.id_stage_i.controller_i.ebrk_force_debug_mode),

.wb_bypass (cv32e40p_wrapper_i.core_i.ex_stage_i.branch_in_ex_i),

.wb_valid (cv32e40p_wrapper_i.core_i.wb_valid),
.wb_reg_addr (cv32e40p_wrapper_i.core_i.regfile_waddr_fw_wb_o),
.wb_reg_we (cv32e40p_wrapper_i.core_i.regfile_we_wb),
.wb_reg_wdata (cv32e40p_wrapper_i.core_i.regfile_wdata),

.imm_u_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_u_type),
.imm_uj_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_uj_type),
.imm_i_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_i_type),
.imm_iz_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_iz_type[11:0]),
.imm_z_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_z_type),
.imm_s_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s_type),
.imm_sb_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_sb_type),
.imm_s2_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s2_type),
.imm_s3_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s3_type),
.imm_vs_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_vs_type),
.imm_vu_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_vu_type),
.imm_shuffle_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_shuffle_type),
.imm_clip_type (cv32e40p_wrapper_i.core_i.id_stage_i.instr[11:7]),
.apu_en_i (cv32e40p_wrapper_i.apu_req),
.apu_singlecycle_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_singlecycle),
.apu_multicycle_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_multicycle),
.apu_rvalid_i (cv32e40p_wrapper_i.apu_rvalid)
.wb_bypass(cv32e40p_wrapper_i.core_i.ex_stage_i.branch_in_ex_i),

.wb_valid (cv32e40p_wrapper_i.core_i.wb_valid),
.wb_reg_addr (cv32e40p_wrapper_i.core_i.regfile_waddr_fw_wb_o),
.wb_reg_we (cv32e40p_wrapper_i.core_i.regfile_we_wb),
.wb_reg_wdata(cv32e40p_wrapper_i.core_i.regfile_wdata),

.imm_u_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_u_type),
.imm_uj_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_uj_type),
.imm_i_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_i_type),
.imm_iz_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_iz_type[11:0]),
.imm_z_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_z_type),
.imm_s_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s_type),
.imm_sb_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_sb_type),
.imm_s2_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s2_type),
.imm_s3_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_s3_type),
.imm_vs_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_vs_type),
.imm_vu_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_vu_type),
.imm_shuffle_type (cv32e40p_wrapper_i.core_i.id_stage_i.imm_shuffle_type),
.imm_clip_type (cv32e40p_wrapper_i.core_i.id_stage_i.instr[11:7]),
.apu_en_i (cv32e40p_wrapper_i.apu_req),
.apu_singlecycle_i(cv32e40p_wrapper_i.core_i.ex_stage_i.apu_singlecycle),
.apu_multicycle_i (cv32e40p_wrapper_i.core_i.ex_stage_i.apu_multicycle),
.apu_rvalid_i (cv32e40p_wrapper_i.apu_rvalid)
);
`endif

Expand All @@ -201,44 +200,44 @@ module cv32e40p_tb_wrapper
.PULP_ZFINX (PULP_ZFINX),
.NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
) cv32e40p_wrapper_i (
.clk_i (clk_i ),
.rst_ni (rst_ni ),

.pulp_clock_en_i (pulp_clock_en_i ),
.scan_cg_en_i (scan_cg_en_i ),

.boot_addr_i (boot_addr_i ),
.mtvec_addr_i (mtvec_addr_i ),
.dm_halt_addr_i (dm_halt_addr_i ),
.hart_id_i (hart_id_i ),
.dm_exception_addr_i (dm_exception_addr_i),

.instr_req_o (instr_req_o ),
.instr_gnt_i (instr_gnt_i ),
.instr_rvalid_i (instr_rvalid_i ),
.instr_addr_o (instr_addr_o ),
.instr_rdata_i (instr_rdata_i ),

.data_req_o (data_req_o ),
.data_gnt_i (data_gnt_i ),
.data_rvalid_i (data_rvalid_i ),
.data_we_o (data_we_o ),
.data_be_o (data_be_o ),
.data_addr_o (data_addr_o ),
.data_wdata_o (data_wdata_o ),
.data_rdata_i (data_rdata_i ),

.irq_i (irq_i ),
.irq_ack_o (irq_ack_o ),
.irq_id_o (irq_id_o ),

.debug_req_i (debug_req_i ),
.debug_havereset_o (debug_havereset_o ),
.debug_running_o (debug_running_o ),
.debug_halted_o (debug_halted_o ),

.fetch_enable_i (fetch_enable_i ),
.core_sleep_o (core_sleep_o )
.clk_i (clk_i),
.rst_ni(rst_ni),

.pulp_clock_en_i(pulp_clock_en_i),
.scan_cg_en_i (scan_cg_en_i),

.boot_addr_i (boot_addr_i),
.mtvec_addr_i (mtvec_addr_i),
.dm_halt_addr_i (dm_halt_addr_i),
.hart_id_i (hart_id_i),
.dm_exception_addr_i(dm_exception_addr_i),

.instr_req_o (instr_req_o),
.instr_gnt_i (instr_gnt_i),
.instr_rvalid_i(instr_rvalid_i),
.instr_addr_o (instr_addr_o),
.instr_rdata_i (instr_rdata_i),

.data_req_o (data_req_o),
.data_gnt_i (data_gnt_i),
.data_rvalid_i(data_rvalid_i),
.data_we_o (data_we_o),
.data_be_o (data_be_o),
.data_addr_o (data_addr_o),
.data_wdata_o (data_wdata_o),
.data_rdata_i (data_rdata_i),

.irq_i (irq_i),
.irq_ack_o(irq_ack_o),
.irq_id_o (irq_id_o),

.debug_req_i (debug_req_i),
.debug_havereset_o(debug_havereset_o),
.debug_running_o (debug_running_o),
.debug_halted_o (debug_halted_o),

.fetch_enable_i(fetch_enable_i),
.core_sleep_o (core_sleep_o)
);

endmodule
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