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Automatic PR dev->master #873

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merged 7 commits into from
Sep 14, 2023
Merged

Automatic PR dev->master #873

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692165c
Adding memory access to rvfi trace log
Sep 7, 2023
d85ea99
RVFI - Better mask for memory access
Sep 12, 2023
531b867
Merge pull request #871 from YoannPruvost/dev_rvfi_trace_log
davideschiavone Sep 12, 2023
479141d
RVFI - better dcsr reporting
Sep 12, 2023
d56010a
RVFI - Improving cv.lbu reporting on corner case
Sep 13, 2023
e1c6e75
Removing unused code
Sep 14, 2023
d0f3305
Merge pull request #872 from YoannPruvost/dev_rvfi_debug
davideschiavone Sep 14, 2023
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46 changes: 29 additions & 17 deletions bhv/cv32e40p_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -158,6 +158,8 @@ module cv32e40p_rvfi
input logic lsu_ready_ex_i,
input logic lsu_ready_wb_i,

input logic [3:0] lsu_data_be_i,

input logic data_req_pmp_i,
input logic data_gnt_pmp_i,
input logic data_rvalid_i,
Expand Down Expand Up @@ -723,17 +725,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
end
end


//FOR DEBUG!!!!!!!!!!!!!!!!!!!!!!
// if(new_rvfi_trace.m_order == 64'h0000_0000_0000_4423) begin
// new_rvfi_trace.m_csr.mcause_rdata = 32'h8000_0010;
// new_rvfi_trace.m_csr.mcause_wdata = 32'h8000_0010;
// new_rvfi_trace.m_csr.mstatus_rdata = 32'h0000_1888;
// new_rvfi_trace.m_csr.mstatus_wdata = 32'h0000_1888;
// new_rvfi_trace.m_csr.mepc_rdata = 32'h0000_554E;
// new_rvfi_trace.m_csr.mepc_wdata = 32'h0000_554E;
// end

rvfi_order = new_rvfi_trace.m_order;
rvfi_pc_rdata = new_rvfi_trace.m_pc_rdata;
rvfi_insn = new_rvfi_trace.m_insn;
Expand Down Expand Up @@ -934,7 +925,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
endfunction

function void dcsr_to_id();
trace_id.m_csr.dcsr_we = r_pipe_freeze_trace.csr.dcsr_we;
trace_id.m_csr.dcsr_wdata = trace_id.m_csr.dcsr_we ? trace_id.m_csr.dcsr_wdata : r_pipe_freeze_trace.csr.dcsr_n;
trace_id.m_csr.dcsr_we = r_pipe_freeze_trace.csr.dcsr_we | trace_id.m_csr.dcsr_we;
trace_id.m_csr.dcsr_rdata = r_pipe_freeze_trace.csr.dcsr_q;
trace_id.m_csr.dcsr_rmask = '1;
trace_id.m_csr.dcsr_wdata = r_pipe_freeze_trace.csr.dcsr_n;
Expand Down Expand Up @@ -1192,6 +1184,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
`CSR_FROM_PIPE(id, dpc)
endfunction

function logic [31:0] be_to_mask(logic [3:0] be);
logic [31:0] mask;
mask[7:0] = be[0] ? 8'hFF : 8'h00;
mask[15:8] = be[0] ? 8'hFF : 8'h00;
mask[23:16] = be[0] ? 8'hFF : 8'h00;
mask[31:24] = be[0] ? 8'hFF : 8'h00;

be_to_mask = mask;
return mask;
endfunction

task compute_pipeline();
bit s_new_valid_insn;
bit s_ex_valid_adjusted;
Expand Down Expand Up @@ -1271,9 +1274,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
`CSR_FROM_PIPE(id, tdata2)
tinfo_to_id();
`CSR_FROM_PIPE(id, mip)
send_rvfi(trace_id);
trace_id.m_valid = 1'b0;
->e_send_rvfi_trace_id_1;
end
end

Expand Down Expand Up @@ -1483,6 +1483,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
if (r_pipe_freeze_trace.csr.we) begin
`CSR_FROM_PIPE(id, dpc)
end

if (r_pipe_freeze_trace.csr.dcsr_we) begin
dcsr_to_id();
end

if (s_fflags_we_non_apu) begin
trace_id.m_fflags_we_non_apu = 1'b1;
end
Expand Down Expand Up @@ -1528,6 +1533,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
end else if (!trace_ex.m_valid & r_pipe_freeze_trace.rf_we_wb & !trace_id.m_ex_fw) begin
trace_id.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
end else if (r_pipe_freeze_trace.rf_we_wb) begin
trace_id.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
trace_id.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
trace_id.m_2_rd_insn = 1'b1;
end

if (r_pipe_freeze_trace.data_req_ex) begin
Expand All @@ -1540,12 +1549,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
cnt_data_req = cnt_data_req + 1;
end
if (!r_pipe_freeze_trace.data_we_ex) begin
trace_id.m_is_load = 1'b1;
trace_id.m_is_load = 1'b1;
trace_id.m_mem.wmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1;
if (r_pipe_freeze_trace.data_misaligned) begin
trace_id.m_data_missaligned = 1'b1;
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
trace_id.m_mem_req_id[0] = cnt_data_req;
end
end else begin
trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1;
end
if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1
trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
Expand Down Expand Up @@ -1662,7 +1674,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
`CSR_FROM_PIPE(id, mcause)
end

if (!s_id_done) begin
if (!s_id_done && r_pipe_freeze_trace.is_decoding) begin
dcsr_to_id();
->e_commit_dpc;
end
Expand Down
24 changes: 23 additions & 1 deletion bhv/cv32e40p_rvfi_trace.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,13 @@ module cv32e40p_rvfi_trace
input logic rvfi_frs1_rvalid,
input logic rvfi_frs2_rvalid,
input logic [31:0] rvfi_frs1_rdata,
input logic [31:0] rvfi_frs2_rdata
input logic [31:0] rvfi_frs2_rdata,

input logic [31:0] rvfi_mem_addr,
input logic [ 3:0] rvfi_mem_rmask,
input logic [ 3:0] rvfi_mem_wmask,
input logic [31:0] rvfi_mem_rdata,
input logic [31:0] rvfi_mem_wdata
);

import cv32e40p_tracer_pkg::*;
Expand Down Expand Up @@ -166,6 +172,21 @@ instr_trace_t trace_retire;
end
endfunction : apply_reg_write

function void apply_mem_access();
mem_acc_t mem_acc;

mem_acc.addr = rvfi_mem_addr;
if (rvfi_mem_wmask) begin
mem_acc.we = 1'b1;
mem_acc.wdata = rvfi_mem_wdata;
trace_retire.mem_access.push_back(mem_acc);
end else if (rvfi_mem_rmask) begin
mem_acc.we = 1'b0;
mem_acc.wdata = 'x;
trace_retire.mem_access.push_back(mem_acc);
end
endfunction : apply_mem_access

// cycle counter
always_ff @(posedge clk_i, negedge rst_ni) begin
if (rst_ni == 1'b0) cycles <= 0;
Expand All @@ -176,6 +197,7 @@ instr_trace_t trace_retire;
if (rvfi_valid) begin
trace_retire = trace_new_instr();
apply_reg_write();
apply_mem_access();
trace_retire.printInstrTrace();
end
end
Expand Down
9 changes: 8 additions & 1 deletion bhv/cv32e40p_tb_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -325,6 +325,8 @@ module cv32e40p_tb_wrapper
.lsu_ready_ex_i (cv32e40p_top_i.core_i.lsu_ready_ex),
.lsu_ready_wb_i (cv32e40p_top_i.core_i.lsu_ready_wb),

.lsu_data_be_i(cv32e40p_top_i.core_i.load_store_unit_i.data_be),

.data_req_pmp_i(cv32e40p_top_i.core_i.data_req_pmp),
.data_gnt_pmp_i(cv32e40p_top_i.core_i.data_gnt_pmp),
.data_rvalid_i(cv32e40p_top_i.core_i.data_rvalid_i),
Expand Down Expand Up @@ -457,7 +459,12 @@ module cv32e40p_tb_wrapper
.rvfi_frs1_rvalid(rvfi_frs1_rvalid),
.rvfi_frs2_rvalid(rvfi_frs2_rvalid),
.rvfi_frs1_rdata(rvfi_frs1_rdata),
.rvfi_frs2_rdata(rvfi_frs2_rdata)
.rvfi_frs2_rdata(rvfi_frs2_rdata),
.rvfi_mem_addr(rvfi_mem_addr),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata)
);
`endif
// Instantiate the Core and the optinal FPU
Expand Down
2 changes: 2 additions & 0 deletions bhv/pipe_freeze_trace.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,7 @@ typedef struct {
logic p_elw_finish;
logic lsu_ready_ex;
logic lsu_ready_wb;
logic [3:0] lsu_data_be;
logic data_req_pmp;
logic data_gnt_pmp;
logic data_rvalid;
Expand Down Expand Up @@ -487,6 +488,7 @@ task monitor_pipeline();
r_pipe_freeze_trace.p_elw_finish = p_elw_finish_i;
r_pipe_freeze_trace.lsu_ready_ex = lsu_ready_ex_i;
r_pipe_freeze_trace.lsu_ready_wb = lsu_ready_wb_i;
r_pipe_freeze_trace.lsu_data_be = lsu_data_be_i;

r_pipe_freeze_trace.data_req_pmp = data_req_pmp_i;
r_pipe_freeze_trace.data_gnt_pmp = data_gnt_pmp_i;
Expand Down
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