Merge pull request #758 from silabs-oysteink/silabs-oysteink_jvg-doc

Updated documentation of JVT CSR alignment from 1024 Bytes to 64 Bytes.
openhwgroup · Jan 9, 2023 · 41188a3 · 41188a3
2 parents 901e9f9 + 40ac9cf
commit 41188a3
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst
@@ -412,9 +412,7 @@ Detailed:
   +----------+------------+-----------------------------------------------------------------------------------------------+
   |   Bit #  | R/W        |           Description                                                                         |
   +==========+============+===============================================================================================+
-  | 31:10    | WARL       | **BASE[31:10]**: Table Jump Base Address, 1024 byte aligned.                                  |
-  +----------+------------+-----------------------------------------------------------------------------------------------+
-  |  9:6     | WARL (0x0) | **BASE[9:6]**: Table Jump Base Address, 1024 byte aligned. ``jvt[9:6]`` is hardwired to 0x0.  |
+  | 31:6     | WARL       | **BASE[31:6]**: Table Jump Base Address, 64 byte aligned.                                     |
   +----------+------------+-----------------------------------------------------------------------------------------------+
   |  5:0     | WARL (0x0) | **MODE**: Jump table mode                                                                     |
   +----------+------------+-----------------------------------------------------------------------------------------------+