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[gen_from_riscv_config] fix access issues for PMP registers, improve …
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…Factorization algorithm , improve csr_updater.yaml, add spike support (#2372)
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@AbdessamiiOukalrazqou
AbdessamiiOukalrazqou authored Jul 21, 2024
1 parent 8c70976 commit 5f86058
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110 changes: 76 additions & 34 deletions config/gen_from_riscv_config/cv32a65x/csr/csr.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,13 @@ Register Summary
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x344 | `MIP <#MIP>`_ | MRW | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x3a0-0x3a3 | `PMPCFG[0-3] <#PMPCFG[0-3]>`_ | MRW | PMP configuration register |
| 0x3a0-0x3a1 | `PMPCFG[0-1] <#PMPCFG[0-1]>`_ | MRW | PMP configuration register |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x3b0-0x3bf | `PMPADDR[0-15] <#PMPADDR[0-15]>`_ | MRW | Physical memory protection address register |
| 0x3a2-0x3af | `PMPCFG[2-15] <#PMPCFG[2-15]>`_ | MRW | PMP configuration register |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x3b0-0x3b7 | `PMPADDR[0-7] <#PMPADDR[0-7]>`_ | MRW | Physical memory protection address register |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x3b8-0x3ef | `PMPADDR[8-63] <#PMPADDR[8-63]>`_ | MRW | Physical memory protection address register |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
| 0x7c0 | `ICACHE <#ICACHE>`_ | MRW | the register controls the operation of the i-cache unit. |
+-------------+---------------------------------------------+-------------+----------------------------------------------------------------------------------------------------+
Expand Down Expand Up @@ -206,15 +210,15 @@ MIE
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 6 | VSTIE | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 7 | MTIE | 0x0 | ROVAR | 0x0 - 0x1 | Machine Timer Interrupt enable. |
| 7 | MTIE | 0x0 | WLRL | 0x0 - 0x1 | Machine Timer Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 8 | UEIE | 0x0 | ROCST | 0x0 | User External Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 9 | SEIE | 0x0 | ROCST | 0x0 | Supervisor External Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 10 | VSEIE | 0x0 | ROCST | 0x0 | VS-level External Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 11 | MEIE | 0x0 | ROVAR | 0x0 - 0x1 | Machine External Interrupt enable. |
| 11 | MEIE | 0x0 | WLRL | 0x0 - 0x1 | Machine External Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
| 12 | SGEIE | 0x0 | ROCST | 0x0 | HS-level External Interrupt enable. |
+---------+--------------+---------------+--------+----------------+---------------------------------------+
Expand Down Expand Up @@ -285,7 +289,7 @@ MHPMEVENT[3-31]
+--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+==========================================================================+
| [31:0] | MHPMEVENT[I] | 0x00000000 | ROCST | 0x00000000 | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
| [31:0] | MHPMEVENT[I] | 0x00000000 | ROCST | 0x0 | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
+--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------+


Expand Down Expand Up @@ -336,7 +340,7 @@ MCAUSE
+--------+----------------+---------------+--------+----------------+-----------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+================+===============+========+================+=====================================================+
| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | 0 - 15 | Encodes the exception code. |
| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | 0x0 - 0x8, 0xb | Encodes the exception code. |
+--------+----------------+---------------+--------+----------------+-----------------------------------------------------+
| 31 | INTERRUPT | 0x0 | WLRL | 0x0 - 0x1 | Indicates whether the trap was due to an interrupt. |
+--------+----------------+---------------+--------+----------------+-----------------------------------------------------+
Expand All @@ -355,7 +359,7 @@ MTVAL
+--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+====================================================================================================+
| [31:0] | MTVAL | 0x00000000 | ROCST | 0x00000000 | The mtval is a warl register that holds the address of the instruction which caused the exception. |
| [31:0] | MTVAL | 0x00000000 | ROCST | 0x0 | The mtval is a warl register that holds the address of the instruction which caused the exception. |
+--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------------------------------+


Expand Down Expand Up @@ -402,33 +406,55 @@ MIP
+---------+--------------+---------------+--------+----------------+----------------------------------------+


.. .. _PMPCFG[0-3]:::
PMPCFG[0-3]
.. .. _PMPCFG[0-1]:::
PMPCFG[0-1]
~~~~~~~~~~~

:Address: 0x3a0-0x3af
:Address: 0x3a0-0x3a1
:Reset Value: 0x00000000
:Privilege: MRW
:Description: PMP configuration register

+---------+-----------------+---------------+--------+----------------+------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+=========+=================+===============+========+================+========================+
| [7:0] | PMP[I*4 + 0]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+-----------------+---------------+--------+----------------+------------------------+
| [15:8] | PMP[I*4 + 1]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+-----------------+---------------+--------+----------------+------------------------+
| [23:16] | PMP[I*4 + 2]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+-----------------+---------------+--------+----------------+------------------------+
| [31:24] | PMP[I*4 + 3]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+-----------------+---------------+--------+----------------+------------------------+


.. .. _PMPADDR[0-15]:::
PMPADDR[0-15]
~~~~~~~~~~~~~
+---------+----------------+---------------+--------+----------------+------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+=========+================+===============+========+================+========================+
| [7:0] | PMP[I*4 +0]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [15:8] | PMP[I*4 +1]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [23:16] | PMP[I*4 +2]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [31:24] | PMP[I*4 +3]CFG | 0x0 | WARL | 0x00 - 0xFF | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+


.. .. _PMPCFG[2-15]:::
PMPCFG[2-15]
~~~~~~~~~~~~

:Address: 0x3a2-0x3af
:Reset Value: 0x00000000
:Privilege: MRW
:Description: PMP configuration register

+---------+----------------+---------------+--------+----------------+------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+=========+================+===============+========+================+========================+
| [7:0] | PMP[I*4 +0]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [15:8] | PMP[I*4 +1]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [23:16] | PMP[I*4 +2]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+
| [31:24] | PMP[I*4 +3]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits |
+---------+----------------+---------------+--------+----------------+------------------------+

:Address: 0x3b0-0x3ef

.. .. _PMPADDR[0-7]:::
PMPADDR[0-7]
~~~~~~~~~~~~

:Address: 0x3b0-0x3b7
:Reset Value: 0x00000000
:Privilege: MRW
:Description: Physical memory protection address register
Expand All @@ -440,6 +466,22 @@ PMPADDR[0-15]
+--------+--------------+---------------+--------+-------------------------+---------------------------------------------+


.. .. _PMPADDR[8-63]:::
PMPADDR[8-63]
~~~~~~~~~~~~~

:Address: 0x3b8-0x3ef
:Reset Value: 0x00000000
:Privilege: MRW
:Description: Physical memory protection address register

+--------+--------------+---------------+--------+----------------+---------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+=============================================+
| [31:0] | PMPADDR[I] | 0x00000000 | ROCST | 0x0 | Physical memory protection address register |
+--------+--------------+---------------+--------+----------------+---------------------------------------------+


.. .. _ICACHE:::
ICACHE
~~~~~~
Expand Down Expand Up @@ -523,7 +565,7 @@ MHPMCOUNTER[3-31]
+--------+----------------+---------------+--------+----------------+---------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+================+===============+========+================+===========================================================================+
| [31:0] | MHPMCOUNTER[I] | 0x00000000 | ROCST | 0x00000000 | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
| [31:0] | MHPMCOUNTER[I] | 0x00000000 | ROCST | 0x0 | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
+--------+----------------+---------------+--------+----------------+---------------------------------------------------------------------------+


Expand Down Expand Up @@ -572,7 +614,7 @@ MHPMCOUNTER[3-31]H
+--------+-----------------+---------------+--------+----------------+----------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+=================+===============+========+================+================================================================+
| [31:0] | MHPMCOUNTER[I]H | 0x00000000 | ROCST | 0x00000000 | The mhpmcounterh returns the upper half word in RV32I systems. |
| [31:0] | MHPMCOUNTER[I]H | 0x00000000 | ROCST | 0x0 | The mhpmcounterh returns the upper half word in RV32I systems. |
+--------+-----------------+---------------+--------+----------------+----------------------------------------------------------------+


Expand All @@ -589,7 +631,7 @@ MVENDORID
+--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+============================================================================================+
| [31:0] | MVENDORID | 0x00000602 | ROCST | 0x00000602 | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
| [31:0] | MVENDORID | 0x00000602 | ROCST | 0x602 | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
+--------+--------------+---------------+--------+----------------+--------------------------------------------------------------------------------------------+


Expand All @@ -606,7 +648,7 @@ MARCHID
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+===============================================================================+
| [31:0] | MARCHID | 0x00000003 | ROCST | 0x00000003 | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
| [31:0] | MARCHID | 0x00000003 | ROCST | 0x3 | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------+


Expand All @@ -623,7 +665,7 @@ MIMPID
+--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+============================================================================+
| [31:0] | MIMPID | 0x00000000 | ROCST | 0x00000000 | Provides a unique encoding of the version of the processor implementation. |
| [31:0] | MIMPID | 0x00000000 | ROCST | 0x0 | Provides a unique encoding of the version of the processor implementation. |
+--------+--------------+---------------+--------+----------------+----------------------------------------------------------------------------+


Expand All @@ -640,7 +682,7 @@ MHARTID
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+=================================================================================================+
| [31:0] | MHARTID | 0x00000000 | ROCST | 0x00000000 | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
| [31:0] | MHARTID | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------------------------+


Expand All @@ -657,6 +699,6 @@ MCONFIGPTR
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------------------------+
| Bits | Field Name | Reset Value | Type | Legal Values | Description |
+========+==============+===============+========+================+=================================================================================================+
| [31:0] | MCONFIGPTR | 0x00000000 | ROCST | 0x00000000 | MXLEN-bit read-only register that holds the physical address of a configuration data structure. |
| [31:0] | MCONFIGPTR | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register that holds the physical address of a configuration data structure. |
+--------+--------------+---------------+--------+----------------+-------------------------------------------------------------------------------------------------+

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