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fix single-step which was x in cv32a65x config and fix mcycle for dou…
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…ble commit (#2369)
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cathales authored Aug 22, 2024
1 parent 12f41b5 commit 76e5b40
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Showing 4 changed files with 8 additions and 3 deletions.
2 changes: 1 addition & 1 deletion core/csr_regfile.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2515,7 +2515,7 @@ module csr_regfile
// determine if mprv needs to be considered if in debug mode
assign mprv = (CVA6Cfg.DebugEn && debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv;
assign debug_mode_o = debug_mode_q;
assign single_step_o = dcsr_q.step;
assign single_step_o = CVA6Cfg.DebugEn ? dcsr_q.step : 1'b0;
assign mcountinhibit_o = {{29 - MHPMCounterNum{1'b0}}, mcountinhibit_q};

// sequential process
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1 change: 1 addition & 0 deletions core/cva6.sv
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Expand Up @@ -1508,6 +1508,7 @@ module cva6
assign halt_acc_ctrl = '0;
assign stall_st_pending_ex = '0;
assign flush_acc = '0;
assign single_step_acc_commit = '0;

// D$ connection is unused
assign dcache_req_ports_acc_cache = '0;
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2 changes: 2 additions & 0 deletions verif/env/uvme/uvme_cva6_env.sv
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Expand Up @@ -174,6 +174,8 @@ function void uvme_cva6_env_c::build_phase(uvm_phase phase);
`uvm_info("CVA6Cfg", $sformatf("Found RTL configuration handle:\n%p", cfg.CVA6Cfg), UVM_DEBUG)
end

cfg.rvfi_cfg.nret = cfg.CVA6Cfg.NrCommitPorts;

if (cfg.enabled) begin
void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt));
if (!cntxt) begin
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6 changes: 4 additions & 2 deletions verif/env/uvme/uvme_cva6_sb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -353,7 +353,7 @@ function bit [XLEN:0] uvme_cva6_sb_c::check_mcycle_h(uvma_isacov_instr_c instr,
overflow = 1;
end
else begin
`uvm_error(get_type_name(), $sformatf("ERROR : No overflow - MCYCLE isn't incremented"))
`uvm_error(get_type_name(), $sformatf("ERROR : No overflow - MCYCLE isn't incremented, %d - %d", mcycle_read, mcycle_prev))
overflow = 0;
end
end
Expand Down Expand Up @@ -484,7 +484,9 @@ task uvme_cva6_sb_c::run_phase(uvm_phase phase);
instr_trn_fifo.get(instr_trn);
check_pc_trap(instr_trn.instr, instr_prev);
check_mepc(instr_trn.instr);
mcycle_update = check_mcycle_h(instr_trn.instr, instr_prev, read_cycle);
if (instr_trn.instr.rvfi.nret_id == 0) begin
mcycle_update = check_mcycle_h(instr_trn.instr, instr_prev, read_cycle);
end
// Move instructions down the pipeline
instr_prev = instr_trn.instr;
end
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