Adding a new configuration file for cv64a60ax and dv target RV64IMAFDC (

#2761)

A new configuration file and core v target is added to start working on a 64 bit CVA6 core.

---------

Co-authored-by: JeanRochCoulon <[email protected]>

config/riscv-config/cv64a60ax/spec/custom_spec.yaml

@@ -0,0 +1,55 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+hart_ids: [0]
+hart0:
+    icache:
+      reset-val: 0x1
+      rv32:
+        accessible: false
+      rv64:
+        accessible: true
+        icache:
+          implemented: true
+          type:
+            rw: true
+          description: bit for cache-enable of instruction cache
+          msb: 0
+          lsb: 0
+          shadow:
+          shadow_type:
+      description: the register controls the operation of the i-cache unit.
+      address: 0x7c0
+      priv_mode: M
+    dcache:
+      reset-val: 0x1
+      rv32:
+        accessible: false
+      rv64:
+        accessible: true
+        dcache:
+          implemented: true
+          type:
+            rw: true
+          description: bit for cache-enable of data cache
+          shadow:
+          shadow_type:
+          msb: 0
+          lsb: 0
+      description: the register controls the operation of the d-cache unit.
+      address: 0x7c1
+      priv_mode: M
+

config/riscv-config/cv64a60ax/spec/debug_spec.yaml

@@ -0,0 +1,168 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+# Updated from CV66 64 CEA - Tanuj Khandelwal - Thales
+
+hart_ids: [0]
+hart0: &hart0
+  Debug_Spec_Version: '1.0.0'
+  supported_xlen: [64]
+  debug_mode: true
+  parking_loop: 0x800
+  dcsr:
+   reset-val: 0x40000413
+   rv64:
+     accessible: true
+     debugver:
+       implemented: true
+       type:
+         ro_constant: 0x4  
+     ebreakvs:
+       implemented: false
+     ebreakvu:
+       implemented: false
+     ebreakm:
+       implemented: true 
+     ebreaks:
+       implemented: true 
+     ebreaku:
+       implemented: true 
+     stepie:
+       implemented: true 
+     stopcount:
+       implemented: true 
+     stoptime:
+       implemented: true 
+     cause:
+       implemented: true 
+       type: 
+         ro_variable: true
+     v:
+       implemented: true 
+     mprven:
+       implemented: true 
+     nmip:
+       implemented: true 
+       type: 
+         ro_variable: true
+     step:
+       implemented: true 
+     prv:
+       implemented: true 
+   rv32:
+     accessible: false
+  dpc: 
+   rv64:
+     accessible: true
+   rv32:
+     accessible: false
+  tselect:
+    rv32:
+      accessible: False
+    rv64:
+      accessible: True
+      type:
+        warl:
+          dependency_fields: []
+          legal:
+            - tselect[63:0] in [0x00000000:0x3]
+          wr_illegal:
+            - unchanged
+  tinfo: #FIXME
+    rv32:
+      accessible: False
+    rv64:
+      accessible: True
+      index_select_reg: tselect
+      index_list:
+        - reset-val: 0x78
+          index_val: 0
+          shadow: 
+          shadow_type:
+          type:
+            ro_constant: 0x78
+        - reset-val: 0x8
+          index_val: 1
+          shadow: 
+          shadow_type:
+          type:
+            ro_constant: 0x8
+        - reset-val: 0x10
+          index_val: 2
+          shadow: 
+          shadow_type:
+          type:
+            ro_constant: 0x10
+  tdata1:
+    rv32:
+      accessible: False
+    rv64:
+      accessible: True
+      index_select_reg: tselect
+      index_list:
+        - reset-val: 0xdeadbeef
+          index_val: 0
+          shadow: 
+          shadow_type:
+          type:
+            ro_constant: 0xdeadbeef
+        - reset-val: 0
+          index_val: 1
+          shadow: 
+          shadow_type:
+          type: &mywarl
+            warl:
+                dependency_fields: []
+                legal:
+                  - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF]
+                wr_illegal:
+                  - Unchanged
+        - reset-val: 0
+          index_val: 2
+          shadow: 
+          shadow_type:
+          type:
+            warl:
+                dependency_fields: []
+                legal:
+                  - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF]
+                wr_illegal:
+                  - Unchanged
+
+                    #FIXME NTO SUPPORTED BY RISCV CNFIG
+                    # tdata2:
+                    #   rv64:
+                    #       accessible: true
+                    #       type:
+                    #           ro_variable: true
+                    #   rv32:
+                    #       accessible: false
+                    # tdata3:
+                    #   rv64:
+                    #       accessible: true
+                    #       type:
+                    #           ro_variable: true
+                    #   rv32:
+                    #       accessible: false
+  dscratch0:
+   rv64:
+     accessible: true
+   rv32:
+     accessible: false
+  dscratch1:
+   rv64:
+     accessible: true
+   rv32:
+     accessible: false