cv32e40p_v1.8.3

What's Changed

• FV Checklist Update by @ntuszynski in #310
• User Manual license headers by @MikeOpenHWGroup in #308
• Checklist completion by @MikeOpenHWGroup in #306
• Record attendance at SW TG of 14 Dec 2020. by @jeremybennett in #316
• cleanup general input for exception/waivers column by @ntuszynski in #317
• Update URL for final reports by @MikeOpenHWGroup in #319
• SignOff IP Checklist by @DBees in #320
• formal verification checklist update by @ntuszynski in #321
• Monthly Software TG report to TWG. by @jeremybennett in #322
• Add checklist process by @DBees in #315
• Add a link to the CVA6 user manual by @MikeOpenHWGroup in #325
• OneSpin results update - 11Jan21 by @ntuszynski in #326
• 🐛 fix #327 by @davideschiavone in #331
• Issue summary by @MikeOpenHWGroup in #329
• Attendance record for SW TG meeting of 11 January 2020 by @jeremybennett in #328
• Summary of issues found for cv32e40p_v1.0.0 by @MikeOpenHWGroup in #332
• Attendance and slides from 2021.01.21 VTG meeting by @MikeOpenHWGroup in #333
• adding Core TG meeting relocation of XPULP slides and minutes by @davideschiavone in #318
• SW TG report for TWG 25 Jan 2021 by @jeremybennett in #335
• Meeting minutes plus presentation by @Silabs-ArjanB in #337
• TWG attendance by @jerryzeng11 in #336
• VTG attendance 2021.02.04 by @MikeOpenHWGroup in #339
• Migrate HW task group meeting minutes by @zarubaf in #334
• Add CVA6 meeting minutes by @zarubaf in #340
• Attendance for SW Task Group meeting of 8 Feb 2021 by @jeremybennett in #344
• Initial PPL for Verilator Modeling for CORE-V MCU and FPGA SoC by @alfredoh1234 in #342
• Updated following TWG meeting of Jan 20 by @DBees in #345
• Fixed: deleted the cv32e40p user manual by @MikeOpenHWGroup in #348
• Added PPL/PL docs for CV32E40X/CV32E40S by @Silabs-ArjanB in #349
• Minor fixes by @Silabs-ArjanB in #350
• TWG Minutes from Jan 25 by @DBees in #352
• Updated according to pre-PPL meeting by @Silabs-ArjanB in #354
• Updates according to PPL/PL presentation in TWG by @Silabs-ArjanB in #355
• Dashboard revision March 2021 by @DBees in #356
• Fix TPL FORCE RISCV by @DBees in #357
• Slides and minutes for March 1 Cores TG meeting by @Silabs-ArjanB in #359
• slides, notes and attendance for 210308 VTG meeting by @strichmo in #362
• CVA6 PL presentation on behalf of J Quevremont by @DBees in #353
• Twg attendance by @jerryzeng11 in #347
• Update CONTRIBUTING with MCCA requirements by @MikeOpenHWGroup in #361
• Added HW TG meeting minutes and reports by @hpollittsmith in #360
• Update cva6_5_2_21.md by @Imperas in #341
• branch and CI documentation for intended GitFlow branch usage in core-v-verif by @strichmo in #367
• Update Dashboard.md by @rickoco in #368
• Re-organisation of program directory into project folders by @DBees in #366
• Added high level project plan for CV32E40X and CV32E40S by @Silabs-ArjanB in #369
• Update dashboard by @DBees in #370
• update branch and ci presentation with new CIs by @strichmo in #372
• Added March 17 HW TG meeting notes by @hpollittsmith in #371
• slides and attended for 210318 VTG for E cores by @strichmo in #373
• Added PA spreadsheets for cv32e40x and cv32e40s by @Silabs-ArjanB in #374
• Attendance at SW TG meeting of 8 March 2021 by @jeremybennett in #375
• TWG minutes, TWG attendance record, create year folders for TG reports by @DBees in #376
• Add PA checklist by @DBees in #377
• Software TG report to TWG meeting 22 March 2021 by @jeremybennett in #378
• Swtg report 22 feb 21 by @jeremybennett in #379
• Update dashboard following March TWG meeting by @DBees in #380
• Remove TravisCI config by @MikeOpenHWGroup in #382
• Initial version with 16nm synthesis data and coremark results by @treforsouthwell in #383
• 2021-04-09 CVA6 meeting minutes by @MikeOpenHWGroup in #384
• Software TG attendance 12 April 2021 by @jeremybennett in #386
• Cores TG minutes plus slides by @Silabs-ArjanB in #387
• update for 210405 VTG e core meeting by @strichmo in #388
• Moved OBI spec to more logical location and added newer revisions by @Silabs-ArjanB in #390
• Virtual perif counter by @silabs-mateilga in #391
• Updated MCU project docs for PL discussion in TWG Apr 26 2021 by @DBees in #392
• Software TG report to TWG 26 April 2021 by @jeremybennett in #393
• Promote MCU Project on Dashboard by @DBees in #394
• Handcar by @MikeOpenHWGroup in #396
• Cores TG minutes by @Silabs-ArjanB in #397
• Verification Strategy update by @MikeOpenHWGroup in #395
• Add TWG Minutes March and April 2021 by @DBees in #398
• slides and attendance for 210506 VTG meeting by @strichmo in #399
• Add cv-x-if folder by @moimfeld in #402
• Project Launch document for Verilator modeling. by @jeremybennett in #404
• Add updated PC and PL template by @DBees in #403
• Attendance for Software TG meeting on 10 May 2021 by @jeremybennett in #400
• Software TG report for TWG 24 May 2021 by @jeremybennett in #405
• minutes of the cv-x-if meeting by @davideschiavone in #406
• slides and notes from VTG June meeting by @strichmo in #407
• updated VTG attendance for 210603 by @strichmo in #408
• Slides and minutes for Cores TG meeting by @Silabs-ArjanB in #409
• Monthly report on Verilator modeling project. by @jeremybennett in #410
• add meeting slides from 06-17-2021 E core status meeting by @strichmo in #413
• Attendance for Software TG meeting on 14 June 2021 by @shangyunhai in #411
• Add 2021-06-16-thales-cva6_reorg slides by @MikeOpenHWGroup in #412
• Attendance at extra SW TG meeting on 21 June 2021. by @jeremybennett in #420
• Create CV32E41P project proposal.md by @tariqkurd-repo in #418
• Add new CV32E40Pv2 Project Concept proposal by @pascalgouedo in #422
• added slide and attendance for 210701 VTG meeting by @strichmo in #423
• Software TG report to TWG on 28 June 2021. by @jeremybennett in #421
• Removed the Verification Strategy by @MikeOpenHWGroup in #419
• Presentations from June 29, 2021 by @DBees in #424
• Cores TG slides and minutes by @Silabs-ArjanB in #425
• Verilator modeling project report to SW TG for July 2021 by @jeremybennett in #426
• Attendance at Software TG meeting 12 July 2021. by @jeremybennett in #427
• Add HAL Project Concept by @DBees in #416
• Added April HW TG notes by @hpollittsmith in #401
• Add Verilator modeling report for HW TG meeting 21 Jul 2021 by @jeremybennett in #428
• Addition of 5 PC and general dashboard cleanup by @DBees in #429
• Fix broken links in dashboard by @DBees in #430
• Add E20 presentation from PC review by @DBees in #432
• Software TG report to TWG. by @jeremybennett in #433
• added Taiga project concept proposal by @e-matthews in #431
• Correct Softwware TG report for July 2021. by @jeremybennett in #434
• Added Cores TG minutes and slides by @Silabs-ArjanB in #435
• Verilator project report to SW TG meeting of 9 Aug 2021. by @jeremybennett in #436
• Add sdk slides by @DBees in #438
• Attendance at Software TG meeting 9 August 2021 by @jeremybennett in #437
• Update dashboard Taiga Aug2021 by @DBees in #439
• Verilator modeling report for HW TG of 18 Aug 2021 by @jeremybennett in #440
• Software TG report for TWG of 23 Aug 2021 by @jeremybennett in #442
• Verilator modeling report to Software TG of 13 Sep 2021. by @jeremybennett in #446
• Added August HW TG meeting notes by @hpollittsmith in #447
• Cores TG minutes plus slides by @Silabs-ArjanB in #448
• Attendance at Software TG meeting of 13 September 2021. by @jeremybennett in #450
• Verilator modeling report for Hardware TG of 15 September 2021. by @jeremybennett in #451
• update slides and attendance for September VTG meetings by @strichmo in #453
• Based Core-V-MCU-SoCat PL Plan.xlsx by @jasperlin05 in #454
• SDK Concept Proposal by @jeremybennett in #455
• Updated version of CV32E40P v2 PC and requirements by @pascalgouedo in #456
• Merge add file byu upload by @jasperlin05 in #458
• Updated SDK concept proposal by @jeremybennett in #462
• added D2D pptx by @davideschiavone in #465
• Add files via upload by @jasperlin05 in #466
• Delete Core-V-MCU-SoC-Plan_V1.2.pod by @jasperlin05 in #467
• Slides presented to CORE-V-MCU team 21-08-25 by @MikeOpenHWGroup in #444
• MT slides for 10.07.2021 VTG meeting by @MikeOpenHWGroup in #468
• Uploading CVA6 PL by @jquevremont in #469
• Attendance at Software TG meeting of 11 October 2021. by @jeremybennett in #471
• Verilator modeling project report for Software TG meeting of 11 Octob… by @jeremybennett in #470
• Report on Verilator modeling to HW Task Group meeting 20 Oct 2021. by @jeremybennett in #472
• update attendance presentations for October VTG meetings by @strichmo in #473
• Added CORE-V-MCU project docs from Oct 25 TWG by @hpollittsmith in #475
• slides and attendance for November VTG by @strichmo in #476
• Add SDK Project to dashboard by @DBees in #477
• Verilator modeling report for the SW TG. by @jeremybennett in #478
• Added CV32E40Pv2 tasks list and their quotation by @pascalgouedo in #479
• ProjectLibre file by @jasperlin05 in #480
• Cores TG minutes plus slides by @Silabs-ArjanB in #481
• Added Nov. 10 project update spreadsheet by @hpollittsmith in #482
• added CORE-V roadmap October 2021 by @davideschiavone in #483
• slides and attendance for 211118 verification e core status meeting by @strichmo in #485
• Cv32e40pv2 plans by @pascalgouedo in #487
• add PL for cv-x-if by @davideschiavone in #486
• Verilator modeling report for Hardware TG of 17 November 2021. by @jeremybennett in #484
• attendance and slides for 211202 VTG meeting by @strichmo in #488
• Cores TG december by @Silabs-ArjanB in #490
• Attendance at Software TG meeting of 8 November 2021. by @jeremybennett in #491
• Attendance at Software TG meeting 10 January 2022. by @jeremybennett in #492
• Add Roadmap presentations and TWG attendance tracker by @DBees in #494
• add_approved_dev-kit_pc by @DBees in #495
• Fix my name. Tariq by @tariqkurd-repo in #489
• TWG November meeting documents by @DBees in #496
• Add instructions for merging branches by @MikeOpenHWGroup in #497
• Delete Core-V-MCU-SoC-Plan_V1.5.pod by @jasperlin05 in #493
• Add files via upload by @jasperlin05 in #499
• Add Gate Comparison spreadsheet by @DBees in #502
• OpenHWGroup TRL3 for COREV RTL IP template checklist by @MikeOpenHWGroup in #498
• Dashboard updates by @DBees in #501
• added minutes for 19/2/21 by @SubhraKantiDas2020 in #358
• Add identification codes by @zarubaf in #443
• Create TWG Meeting Folder Jan2022 by @DBees in #503
• Core-V MCU UVM Environment Project Proposal by @datum-dpoulin in #504
• Uploaded PL file by @LeeHoff in #505
• February project report for Verilator modeling project by @jeremybennett in #507
• CVA6 PA (plan approved) 2022 document by @jquevremont in #508
• Reorg directories and add CORE-V-eXtension-Interface by @MikeOpenHWGroup in #509
• Solve more TBDs. by @jquevremont in #511
• Updated OBI spec (backward compatible) by @Silabs-ArjanB in #512
• Updated after an external review by @jquevremont in #513
• Review at CVA6 project meeting by @jquevremont in #514
• OBI v1.4 spec by @Silabs-ArjanB in #515
• Remove spaces from filenames by @MikeOpenHWGroup in #510
• Add attendance from Software TG meeting of 14 Feb 2021. by @jeremybennett in #516
• Attendance at Software TG meeting of 14 March 2022. by @jeremybennett in #518
• CSR Access Modes and UVM Agents by @MikeOpenHWGroup in #517
• draft index.rst for CORE-V Docs by @rickoco in #521
• Added Cores TG slides and minutes for February and April by @Silabs-ArjanB in #522
• Gitlab-CI by @MikeOpenHWGroup in #520
• ImperasDV overview for OpenHW CV32E20 Collaboration by @MikeOpenHWGroup in #519
• Update CVA6-plan-approved-2022.md by @jquevremont in #523
• Git101 by @MikeOpenHWGroup in #524
• Add Writting Tests for CORE-V-VERIF by @MikeOpenHWGroup in #526
• Update Dashboard by @jquevremont in #525
• Attendance at Software TG meeting of 11 April 2022. by @jeremybennett in #528
• Attendance at Software TG meeting of 9 May 2022. by @jeremybennett in #529
• add slides from xif 'coop' discussion by @silabs-robin in #530
• Attendance for 11 Jul 2022 Software TG meeting. by @jeremybennett in #533
• Version 1.5.0 of OBI by @Silabs-ArjanB in #535
• CV32E40P v2 presentations by @MikeOpenHWGroup in #534
• E40 pv2 presentation by @MikeOpenHWGroup in #532
• Update twg attendance by @DBees in #531
• update cores.rst by @davideschiavone in #527
• CV32E40P verif updates by @MikeOpenHWGroup in #536
• Meeting minutes Silabs 2022.24.08 by @silabs-hfegran in #537
• Adding the OpenHW mapping of TRLs by @jquevremont in #539
• Add CORE-V-L1-DCACHE Project Concept into the CORE-V-DOCS program folder by @cfuguet in #541
• New dashboard sorted by TG and able to be edited in Excel by @DBees in #540
• Cv32e40pv2 plans by @pascalgouedo in #543
• Dashboard: fix link to the project concept of the CORE-V-L1DCACHE by @cfuguet in #544
• Attendance at Software TG meeting 8 August. by @jeremybennett in #545
• Attendance at Software TG meeting 10 October 2022. by @jeremybennett in #546
• Added approved ARVM project concept by @simon5656 in #547
• Slides for Cores TG of October by @Silabs-ArjanB in #548
• Prepare new structure by @DBees in #550
• Add project concept for CORE-V QEMU by @liweiwei90 in #551
• New vtg documents structure by @simon5656 in #553
• Slides of November Cores TG meeting by @Silabs-ArjanB in #555
• Adding project monthly report template by @DBees in #554
• added this months Nov 22 reports by @simon5656 in #556
• Update to distinguish CV32E40Pv1 and v2 User Manuals by @pascalgouedo in #562
• Attendance at SW Task Group of 14 Nov 2022. by @jeremybennett in #564
• Create Trusted MCU Project Concept Proposal by @abberthe in #563
• Updated E41P Project Proposal by @MarkHillHuawei in #566
• Initial draft of LLVM PL proposal by @jeremybennett in #560
• Test project concept document for CORE-V-WALLY by @davidharrishmc in #568
• Sample concept document by @stineje in #569
• Attendance at Software TG meeting of 9 Jan 2023. by @jeremybennett in #570
• Update to Project Concept/Launch for OpenHWGroup by @stineje in #573
• Jan Update by @simon5656 in #574
• OpenHW CORE-V L1DCACHE - Project Launch Document by @cfuguet in #565
• CV32E40Pv2 Plan Approved proposal by @pascalgouedo in #575
• Update slides for TWG meeting on January 23, 2023 by @stineje in #576
• Two CVA6 presentations that can be of interest for a larger audience by @jquevremont in #558
• Remove verbiage about TRL5 and keep TRL3 objectives by @stineje in #577
• Create cv32a6_v0.1.0_verif_KOM_minutes.md by @JeanRochCoulon in #579
• Clean-up use of GitHub Markdown format by @MikeOpenHWGroup in #580
• Cores TG meeting of February 2023 by @Silabs-ArjanB in #581
• Initial draft of CV32E40Pv2 LLVM Plan Approved 2023 by @ChunyuLiao in #561
• Create folder for CORE-V Trusted MCU status report by @abberthe in #582
• Project Concept for CORE-V CVA6-H by @sandro2pinto in #585
• March2023dashboard by @DBees in #584
• Updated PA & PL for FreeRTOS by @n9wxu in #583
• initial version of force-riscv project proposal by @hanfeng0114 in #587
• Add attendance at Software TG meeting of 13 March 2023 by @jeremybennett in #589
• Updated PA and PF dates for CV32E40Pv2 Plan Approved by @pascalgouedo in #588
• Ohw lee 04042023 by @LeeHoff in #590
• Move TRL-5 reports from CORE-V-VERIF to PROGRAMS by @MikeOpenHWGroup in #592
• Move milestone directory under Project-Description-and-Plans by @MikeOpenHWGroup in #593
• Create a new Plan Approved template by @DBees in #591
• First draft proposal for CORE-V 180 MCU by @jpc-lip6 in #595
• Attendance for Software TG meeting 8 May 2023 by @jeremybennett in #597
• Update core-v-docs RTD project to provide an up to date index by @DBees in #599
• Attendance at Software TG meeting of 10 July 2023 by @jeremybennett in #601
• add read the docs yaml file to core-v-docs project by @DBees in #608
• Fixing up read the docs project by @DBees in #609
• update image files by @DBees in #610
• CVA6 2023-2024 workplan (refresh of 2022 PA gate) by @jquevremont in #598
• Restructured dashboard for review by TWG by @DBees in #612
• Update CVA6-plan-approved-2023-2024.md by @jquevremont in #614
• [CV-DV-UTILS] Added initial project commit MD file by @adrian-cea in #611
• CV-Mesh PC/PL by @Jbalkind in #607
• PA for CVA6 FreeRTOS support by @anjaliigedam in #606
• Draft PL and PA documents for Verilator modeling. by @jeremybennett in #596
• Tighty coupled cache coherence for CVA6 by @suppamax in #615
• Create OpenSourceDevelopmentOpenHWGroup.md by @MikeOpenHWGroup in #616
• Add CORE-V-VISION-APU to dashboard, left off previously by oversight by @DBees in #617
• CVA6 dual issue by @cathales in #618
• Dashboard sep2023 update by @DBees in #619
• Attendance at Software TG of 11 Sep 2023. by @jeremybennett in #620
• PL: CVA6 dual issue by @cathales in #623
• Create stand-alone TRL-5 templates by @MikeOpenHWGroup in #625
• PL: CVA6 dual-issue: add documentation and done criteria by @cathales in #624
• CV-HPDcache plan approve document by @cfuguet in #622
• Added project concept for CV-X-IF extension interface by @christian-herber-nxp in #621
• Updates to Dashboard after Sep 2023 meeting by @DBees in #626
• Added cores TG slides (removed out of date core overview) by @Silabs-ArjanB in #628
• Update PlanApprove_CV-HPDcache.md by @cfuguet in #629
• Added TWG presentation of 2023/10/23 by @jpc-lip6 in #631
• Dashboard sep2023 by @DBees in #630
• Attendance at Software TG of 13 Nov 2023. by @PaoloS02 in #633
• Update details of CORE-V LLVM Tools projects in the dashboard. by @PaoloS02 in #632
• Adding Polara devkit project concept document as voted on. by @francoislp in #637
• adding polara-devkit and cva6-platform to dashboard by @DBees in #638
• Updated CV32E40Pv2 PF Estimate by @pascalgouedo in #639
• Arjan b ctgdec by @Silabs-ArjanB in #640
• Initial version of the Polara Development Board PL document. by @francoislp in #641
• Updating readthedocs yaml file to specify build os by @DBees in #647
• Fix up requirements by @MikeOpenHWGroup in #648
• Cores TG slides February 2024 by @Silabs-ArjanB in #649
• CVA6 Platform PC by @Jbalkind in #651
• Initial version of Project Concept for CV32E40PX by @MPEZZIN in #634
• Cores TG slides March 2024 by @Silabs-ArjanB in #652
• Attendance at Software TG of 11 Mar 2024. by @PaoloS02 in #653
• Add instructions for viewing the coverage results. by @MikeOpenHWGroup in #655
• Updated CVA6 PA document by @jquevremont in #650
• CVE20 monthly report May 2024 by @DBees in #659
• Cores TG May 2024 by @Silabs-ArjanB in #660
• Update PA approval status by @jquevremont in #658
• Create interconnect task group subfolder and upload minutes by @cfuguet in #663
• Initial Milestone Reports for CV32E40Pv2 at RTL tag cv32e40p_v1.8.1 by @dd-BeeNee in #665
• Fix markdown formatting by @MikeOpenHWGroup in #666
• Add short summary table for non-specialists to convey quickly what the results are by @dd-BeeNee in #667
• 2024 Plan Approve for CV32E20 by @DBees in #654
• Adding CV32E40Pv2 Design issues list by @pascalgouedo in #668
• CV32E40Pv2 verification: refresh the coverage reports and documentation. by @dd-BeeNee in #669
• June 2024 monthly report CVE20 by @DBees in #670
• Rename directory RTL_Freeze_v2.0.0 to RTL_v1.8.0 by @dd-BeeNee in #671
• CV32E40Pv2 checklist software tab updated with informations from Embecosm. by @pascalgouedo in #672
• Cores TG June 2024 by @Silabs-ArjanB in #673
• Refresh RTL Code Coverage reports with newly proven waivers, and update documentation. by @dd-BeeNee in #675
• CV32E40Pv2 Design issues list: updated all remaining opened issues. by @pascalgouedo in #674
• Adding Project Framework presentation by @DBees in #676
• Short description of how we use project boards in OpenHW Group by @DBees in #678
• Create CV32E40Pv2_not_verified_features.xlsx by @XavierAubert in #677
• Holes and waivers lists updated. by @pascalgouedo in #679
• First version of MCU/DevkitV2 PL 2024. Needs work, do not merge yet. by @DBees in #662
• A bunch of updates for CV32E40Pv2 reports. by @pascalgouedo in #680
• CV32E40Pv2 RISC-V ISA Formal verif reports addition and update of RTL Design tab in RTL Freeze checklist by @pascalgouedo in #681
• CV32E40Pv2 files updates by @pascalgouedo in #682
• Cores TG slides July 2024 by @Silabs-ArjanB in #683
• CV32E40Pv2 documents and reports updates by @pascalgouedo in #684
• CV32E40Pv2: Added Siemens Questa Processor in index.html by @pascalgouedo in #685
• CV32E40Pv2 index.html updates. by @pascalgouedo in #686
• Corrected wrong CV32E40Pv2 non-regression numbers. by @pascalgouedo in #687
• Final CV32E40Pv2 RISC-V ISA Formal Verification Properties status by @pascalgouedo in #688
• Add attendance of 2024-07-08 SW TG meeting. by @PaoloS02 in #689
• Update CV32E40Pv2_regression_known_failure.xlsx by @XavierAubert in #690
• Final update with issues numbers in CV32E40Pv2 waiver list file. by @pascalgouedo in #691
• CV32E40Pv2: All links updated to cv32e40p_v1.8.3 tag for the 3 target repos (core-v-docs, cv32e40p, core-v-verif). by @pascalgouedo in #692
• CV32E40Pv2 final updates. by @pascalgouedo in #693

Full Changelog: cv32e40p_v1.0.0...cv32e40p_v1.8.3