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    14 repositories

    • fusesoc-cores

      Public
      FuseSoC standard core library
      32•112•0•8•Updated Oct 16, 2024Oct 16, 2024

    • cdc_utils

      Public
      Verilog CDC implementations
      Verilog
      •0•2•2•0•Updated Sep 18, 2024Sep 18, 2024

    • fusesoc-generators

      Public
      A collection of core generators to use with FuseSoC
      Python
      •
      MIT License
      •12•13•1•2•Updated Aug 23, 2024Aug 23, 2024

    • blinky

      Public
      Example LED blinking project for your FPGA dev board of choice
      Tcl
      •
      MIT License
      •71•164•5•4•Updated Aug 21, 2024Aug 21, 2024

    • wb_common

      Public
      Common constants and functions for wishbone buses
      Verilog
      •
      ISC License
      •2•3•0•0•Updated Jul 29, 2024Jul 29, 2024

    • fusesoc.github.io

      Public
      Ruby
      •5•18•1•0•Updated Aug 8, 2023Aug 8, 2023

    • docker-openlane-sky130

      Public
      Build recipe creating Docker image with OpenLANE + Sky130 PDK
      Dockerfile
      •0•1•1•0•Updated Jan 4, 2022Jan 4, 2022

    • vlog_tb_utils

      Public
      Verilog test bench utilities
      Verilog
      •
      ISC License
      •2•3•0•0•Updated Sep 29, 2021Sep 29, 2021

    • fusesoc-runner

      Public
      Run fusesoc on other machines, clusters, etc.
      0•0•0•0•Updated Feb 12, 2021Feb 12, 2021

    • elf-loader

      Public
      VPI library to load ELF files from verilog test benches
      C
      •2•8•1•0•Updated Feb 11, 2021Feb 11, 2021

    • tiny-cores

      Public
      Collection of assorted small cores
      Verilog
      •3•11•1•0•Updated Oct 6, 2020Oct 6, 2020

    • sd_device

      Public
      SD device emulator from ProjectVault
      Verilog
      •
      Apache License 2.0
      •5•14•1•0•Updated Sep 24, 2019Sep 24, 2019

    • wb_altera_ddr_wrapper

      Public
      Altera DDR controller wrapper with multiple wishbone slave ports
      Verilog
      •1•7•0•0•Updated Mar 24, 2018Mar 24, 2018

    • wb_ram

      Public
      On-chip RAM with Wishbone interface
      Verilog
      •
      ISC License
      •3•8•1•0•Updated Feb 8, 2017Feb 8, 2017