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    292 repositories

    • hwpe-datamover-example

      Public
      This is an example of an HCI-based HWPE used simply as a data mover.
      C
      •
      Other
      •2•0•0•1•Updated Oct 30, 2024Oct 30, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •45•275•3•7•Updated Oct 30, 2024Oct 30, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •132•368•63•10•Updated Oct 30, 2024Oct 30, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •46•194•7•24•Updated Oct 30, 2024Oct 30, 2024

    • chimera

      Public
      Python
      •
      Other
      •1•9•9•2•Updated Oct 30, 2024Oct 30, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •2•17•1•1•Updated Oct 30, 2024Oct 30, 2024

    • redmule

      Public
      SystemVerilog
      •
      Other
      •12•33•1•5•Updated Oct 30, 2024Oct 30, 2024

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •1•1•4•3•Updated Oct 30, 2024Oct 30, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •3•9•0•2•Updated Oct 30, 2024Oct 30, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •17•72•1•2•Updated Oct 30, 2024Oct 30, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •262•1.1k•42•14•Updated Oct 30, 2024Oct 30, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Oct 29, 2024Oct 29, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •15•26•4•3•Updated Oct 29, 2024Oct 29, 2024

    • Deeploy

      Public
      ONNX-to-C Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •6•14•1•4•Updated Oct 29, 2024Oct 29, 2024

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •2•18•1•3•Updated Oct 28, 2024Oct 28, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•507•29•7•Updated Oct 28, 2024Oct 28, 2024

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •764•1•0•1•Updated Oct 25, 2024Oct 25, 2024

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •165•385•124•3•Updated Oct 25, 2024Oct 25, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •21•132•10•4•Updated Oct 24, 2024Oct 24, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •28•90•7•8•Updated Oct 24, 2024Oct 24, 2024

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •300•7•0•4•Updated Oct 24, 2024Oct 24, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •685•16•1•9•Updated Oct 24, 2024Oct 24, 2024

    • riscv-gnu-toolchain

      Public
      GNU toolchain for PULP and RISC-V
      C
      •
      Other
      •7•9•0•2•Updated Oct 24, 2024Oct 24, 2024

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •1•9•0•3•Updated Oct 23, 2024Oct 23, 2024

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •9•17•0•0•Updated Oct 23, 2024Oct 23, 2024

    • regression_tests

      Public
      C
      •15•5•3•1•Updated Oct 22, 2024Oct 22, 2024

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •30•28•1•5•Updated Oct 22, 2024Oct 22, 2024

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •37•245•23•3•Updated Oct 22, 2024Oct 22, 2024

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •2•19•4•1•Updated Oct 21, 2024Oct 21, 2024

    • morty

      Public
      A SystemVerilog source file pickler.
      rustpicklersrickandmortysystemverilog-hdl
      Rust
      •
      Apache License 2.0
      •5•51•8•2•Updated Oct 20, 2024Oct 20, 2024