Merge pull request #771 from os-fpga/EDA-3158

Handling inout port after flattening wrapper

CMakeLists.txt

@@ -274,6 +274,7 @@ add_custom_target(
     COMMAND $(MAKE) install ${YOSYS_RS_PLUGIN_MK_ARGS}
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/design_edit
     COMMENT "Compile Yosys Design Edit plugin with given Makefile"
+    DEPENDS GeneratePrimitive
 )
 add_custom_target(
     yosys-rs-plugin_clean
@@ -298,7 +299,6 @@ add_dependencies(yosys_clean yosys-rs-plugin_clean)
 
 add_dependencies(pow_extract yosys)
 add_dependencies(yosys_clean pow_extract_clean)
-add_dependencies(design_edit rs_primitive)
 add_dependencies(design_edit yosys )
 add_dependencies(yosys_clean design_edit_clean)
 

design_edit/src/rs_design_edit.cc

@@ -90,6 +90,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
   std::unordered_set<Wire *> orig_intermediate_wires;
   std::unordered_set<Wire *> interface_intermediate_wires;
   std::map<RTLIL::SigBit, std::vector<RTLIL::Wire *>> io_prim_conn;
+  std::map<RTLIL::SigBit, RTLIL::SigBit> inout_conn_map;
   pool<SigBit> prim_out_bits;
   pool<SigBit> unused_prim_outs;
   pool<SigBit> used_bits;
@@ -585,6 +586,57 @@ struct DesignEditRapidSilicon : public ScriptPass {
     }
   }
 
+  void handle_inout_connection(Module* mod)
+  {
+    for(auto &conn : mod->connections())
+      {
+        std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
+        std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
+        bool remove_conn = false;
+        for (size_t i = 0; i < conn_lhs.size(); ++i)
+        {
+          if (conn_rhs[i].wire != nullptr)
+            if (conn_rhs[i].wire->port_input && conn_rhs[i].wire->port_output)
+            {
+              inout_conn_map[conn_lhs[i]] = conn_rhs[i];
+              remove_conn = true;
+            }
+        }
+        if (remove_conn)
+        {
+          connections_to_remove.insert(conn);
+        }
+      }
+
+      remove_extra_conns(mod);
+      connections_to_remove.clear();
+
+      for (auto cell : mod->cells())
+      {
+        for (auto conn : cell->connections())
+        {
+          IdString portName = conn.first;
+          bool unset_port = true;
+          RTLIL::SigSpec sigspec;
+          for (SigBit bit : conn.second)
+          {
+            if (inout_conn_map.count(bit) > 0)
+            {
+              if (unset_port)
+              {
+                cell->unsetPort(portName);
+                unset_port = false;
+              }
+              sigspec.append(inout_conn_map[bit]);
+            } else {
+              sigspec.append(bit);
+            }
+          }
+          if (!unset_port) cell->setPort(portName, sigspec);
+        }
+      }
+  }
+
   void process_wire(Cell *cell, const IdString &portName, RTLIL::Wire *wire) {
     if (cell->input(portName)) {
       if (wire->port_input) {
@@ -1735,6 +1787,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
       new_design->add(interface_mod);
     }
     Pass::call(new_design, "flatten");
+    handle_inout_connection(wrapper_mod);
 
     for (auto file : wrapper_files) {
       std::string extension = get_extension(file);