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Failing designs are removed from golden suite
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@komalinayat
komalinayat committed Oct 13, 2023
1 parent 7706bfe commit 514b929
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Showing 2 changed files with 2 additions and 82 deletions.
4 changes: 2 additions & 2 deletions scripts/synth/synthesis.py
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Original file line number Diff line number Diff line change
Expand Up @@ -440,7 +440,7 @@ def run_benchmark_with_vivado(benchmark, vivado_file_template,
logger.error('Failed to execute synthesis of {0} for configuration '
'{1}:\n {2}'.format(benchmark["name"], cfg_name,
traceback.format_exc()))
#### DIAMOND

def run_benchmark_with_diamond(benchmark, diamond_file_template,
config_run_dir_base, cfg_name, timeout):
try:
Expand All @@ -461,7 +461,7 @@ def run_benchmark_with_diamond(benchmark, diamond_file_template,
logger.error('Failed to execute synthesis of {0} for configuration '
'{1}:\n {2}'.format(benchmark["name"], cfg_name,
traceback.format_exc()))
### DIAMOND

def create_file_from_template(file_template, replacements, resulting_file):
replacements = dict((re.escape(k), v) for k, v in replacements.items())
pattern = re.compile("|".join(replacements.keys()))
Expand Down
80 changes: 0 additions & 80 deletions suites/Golden/Golden_synth_rs_ade_with_bram_with_dsp.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,26 +34,11 @@
"rtl_path": "RTL_Benchmark/Verilog/ql_design/main_loop_synth/rtl",
"top_module": "main_loop"
},
{
"name": "twofish_128",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_128",
"top_module": "twofish_whit_keysched128"
},
{
"name": "twofish_256",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_256",
"top_module": "twofish_whit_keysched256"
},
{
"name": "cf_rca_16",
"rtl_path": "RTL_Benchmark/Verilog/ql_design/cf_rca_16/rtl",
"top_module": "top"
},
{
"name": "twofish_192",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_192",
"top_module": "twofish_whit_keysched192"
},
{
"name": "smithwaterman",
"rtl_path": "RTL_Benchmark/Verilog/ql_design/smithwaterman/rtl",
Expand All @@ -64,11 +49,6 @@
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b19/rtl",
"top_module": "b19"
},
{
"name": "rsa",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/rsa/trunk/rtl/vhdl",
"top_module": "RSACypher"
},
{
"name": "mem_ctl",
"rtl_path": "RTL_Benchmark/Verilog/EPFL/mem_ctrl/rtl",
Expand Down Expand Up @@ -104,11 +84,6 @@
"rtl_path": "RTL_Benchmark/Verilog/Cores/crypto_core/des/trunk/rtl/verilog",
"top_module": "des3"
},
{
"name": "kmac",
"rtl_path": "RTL_Benchmark/SVerilog/opentitan/ip/kmac/rtl",
"top_module": "kmac"
},
{
"name": "xbar_main",
"rtl_path": "RTL_Benchmark/SVerilog/top_earlgrey/xbar_main/rtl",
Expand All @@ -129,11 +104,6 @@
"rtl_path": "RTL_Benchmark/SVerilog/Cores/crypto_core/aes-128-ecb-encoder/trunk/src",
"top_module": "aes128_enc"
},
{
"name": "rc4-prbs",
"rtl_path": "RTL_Benchmark/Verilog/Cores/crypto_core/rc4-prbs/trunk",
"top_module": "rc4"
},
{
"name": "aes_crypro_core",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/aes_crypto_core/rtl/src",
Expand Down Expand Up @@ -209,11 +179,6 @@
"rtl_path": "RTL_Benchmark/Verilog/EPFL/voter/rtl",
"top_module": "top"
},
{
"name": "lsu",
"rtl_path": "RTL_Benchmark/SVerilog/Cores/Cores-SweRV-EL2/design/lsu",
"top_module": "el2_lsu"
},
{
"name": "dec",
"rtl_path": "RTL_Benchmark/SVerilog/Cores/Cores-SweRV-EL2/design/dec",
Expand Down Expand Up @@ -284,11 +249,6 @@
"rtl_path": "RTL_Benchmark/Verilog/Gate_Level_Netlist/alu4/rtl",
"top_module": "alu4"
},
{
"name": "b15",
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b15/rtl",
"top_module": "b15"
},
{
"name": "b22",
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/i99t/b22/rtl",
Expand Down Expand Up @@ -419,11 +379,6 @@
"rtl_path": "RTL_Benchmark/Verilog/ql_design/conv2d/rtl",
"top_module": "conv2d"
},
{
"name": "salsa20",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/salsa20/trunk/rtl",
"top_module": "salsaa"
},
{
"name": "spi",
"rtl_path": "RTL_Benchmark/Verilog/iwls2005_designs/spi/rtl",
Expand Down Expand Up @@ -484,11 +439,6 @@
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/nfcc/trunk/kasumi",
"top_module": "kasumi"
},
{
"name": "wrapper_KeyExpantion",
"rtl_path": "RTL_Benchmark/Verilog/ql_design/KeyExpantion/wrapper_rtl",
"top_module": "wrapper_KeyExpantion"
},
{
"name": "osc_alu",
"rtl_path": "RTL_Benchmark/Verilog/ql_design/osc_alu/rtl",
Expand Down Expand Up @@ -609,11 +559,6 @@
"rtl_path": "RTL_Benchmark/other/cryptosorter/trunk/memocodeDesignContest2008/aesCorePipelined",
"top_module": "aes_pipelined_cipher_top"
},
{
"name": "aes",
"rtl_path": "RTL_Benchmark/SVerilog/opentitan/ip/aes/rtl",
"top_module": "aes"
},
{
"name": "tseng",
"rtl_path": "RTL_Benchmark/Verilog/Gate_Level_Netlist/tseng/rtl",
Expand Down Expand Up @@ -799,11 +744,6 @@
"rtl_path": "RTL_Benchmark/SVerilog/opentitan/ip/edn/rtl",
"top_module": "edn"
},
{
"name": "threeasc_key_schedule",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/key_schedule/src",
"top_module": "key_schedule"
},
{
"name": "b04",
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b04/rtl",
Expand Down Expand Up @@ -864,16 +804,6 @@
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b13/rtl",
"top_module": "b13"
},
{
"name": "threeasc_aes_c_1",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/aes_c_1/src",
"top_module": "aes_fsm_enc"
},
{
"name": "b08",
"rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b08/rtl",
"top_module": "b08"
},
{
"name": "lookahead_XY_router",
"rtl_path": "RTL_Benchmark/Verilog/EPFL/lookahead_XY_router/rtl",
Expand Down Expand Up @@ -924,11 +854,6 @@
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/aes_c_2/src",
"top_module": "aes_fsm_enc"
},
{
"name": "threeasc_aes_c_3",
"rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/aes_c_3/src",
"top_module": "aes_fsm_enc"
},
{
"name": "adder_128",
"rtl_path": "RTL_Benchmark/Verilog/ql_design/adder_128",
Expand Down Expand Up @@ -1247,11 +1172,6 @@
"rtl_path": "RTL_Benchmark/Verilog/yosys_validation/DSP_Designs/accumulator",
"top_module": "accumulator"
},
{
"name" : "add_output_of_four_multipliers",
"rtl_path": "RTL_Benchmark/Verilog/yosys_validation/DSP_Designs/add_output_of_four_multipliers",
"top_module": "add_output_of_four_multipliers"
},
{
"name" : "add_shifted_input_to_the_mul_output",
"rtl_path": "RTL_Benchmark/Verilog/yosys_validation/DSP_Designs/add_shifted_input_to_the_mul_output",
Expand Down

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