Merge pull request #533 from os-fpga/power_extraction_tool

Merge power data extraction tool in main branch

CMakeLists.txt

@@ -31,6 +31,7 @@ list(APPEND YOSYS_VERIFIC_RS_RECURSIVE_SUBSYTEMS
     yosys
     yosys-plugins
     yosys-rs-plugin
+    pow_extract
     )
 
 if (NOT RAPTOR)
@@ -249,15 +250,30 @@ add_custom_target(
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-rs-plugin
     COMMENT "Compile Yosys RS plugin with given Makefile"
 )
+add_custom_target(
+    pow_extract ALL
+    COMMAND $(MAKE) install ${YOSYS_RS_PLUGIN_MK_ARGS}
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/pow_extract
+    COMMENT "Compile Yosys power estimator plugin with given Makefile"
+)
 add_custom_target(
     yosys-rs-plugin_clean
     COMMAND $(MAKE) clean ${YOSYS_RS_PLUGIN_MK_ARGS}
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-rs-plugin
     COMMENT "Clean Yosys RS plugin with given Makefile"
 )
+add_custom_target(
+    pow_extract_clean
+    COMMAND $(MAKE) clean ${YOSYS_RS_PLUGIN_MK_ARGS}
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/pow_extract
+    COMMENT "Clean Yosys power estimator with given Makefile"
+)
 add_dependencies(yosys-rs-plugin yosys)
 add_dependencies(yosys_clean yosys-rs-plugin_clean)
 
+add_dependencies(pow_extract yosys)
+add_dependencies(yosys_clean pow_extract_clean)
+
 add_custom_target(
     clean_yosys_verific_rs
     COMMAND $(MAKE) yosys_clean

pow_extract/Makefile

@@ -0,0 +1,130 @@
+# Copyright (C) 2022 RapidSilicon..
+
+# Either find yosys in system and use its path or use the given path
+YOSYS_PATH ?= $(realpath $(dir $(shell which yosys))/..)
+
+# Find yosys-config, throw an error if not found
+YOSYS_CONFIG ?= $(YOSYS_PATH)/bin/yosys-config
+ifeq (,$(wildcard $(YOSYS_CONFIG)))
+$(error "Didn't find 'yosys-config' under '$(YOSYS_PATH)'")
+endif
+
+CXX ?= $(shell $(YOSYS_CONFIG) --cxx)
+CXXFLAGS ?= $(shell $(YOSYS_CONFIG) --cxxflags) #-DSDC_DEBUG
+LDFLAGS ?= $(shell $(YOSYS_CONFIG) --ldflags)
+LDLIBS ?= $(shell $(YOSYS_CONFIG) --ldlibs)
+PLUGINS_DIR ?= $(shell $(YOSYS_CONFIG) --datdir)/plugins
+DATA_DIR ?= $(shell $(YOSYS_CONFIG) --datdir)
+EXTRA_FLAGS ?=
+
+COMMON			= ../yosys-rs-plugin/common
+GENESIS			= ../yosys-rs-plugin/genesis
+GENESIS2		= ../yosys-rs-plugin/genesis2
+GENESIS3		= ../yosys-rs-plugin/genesis3
+VERILOG_MODULES	= $(COMMON)/cells_sim.v \
+				  $(COMMON)/simlib.v \
+				  $(GENESIS)/cells_sim.v \
+				  $(GENESIS)/dsp_sim.v \
+				  $(GENESIS)/ffs_map.v \
+				  $(GENESIS)/dsp_map.v \
+				  $(GENESIS)/dsp_final_map.v \
+				  $(GENESIS)/arith_map.v \
+				  $(GENESIS)/all_arith_map.v \
+				  $(GENESIS)/brams_map.v \
+				  $(GENESIS)/brams_map_new.v \
+				  $(GENESIS)/brams_final_map.v \
+				  $(GENESIS)/brams_final_map_new.v \
+				  $(GENESIS)/brams.txt \
+				  $(GENESIS)/brams_new.txt \
+				  $(GENESIS)/brams_async.txt \
+				  $(GENESIS)/TDP18K_FIFO.v \
+				  $(GENESIS)/sram1024x18.v \
+				  $(GENESIS)/ufifo_ctl.v \
+				  $(GENESIS)/cells_sim.vhd \
+				  $(GENESIS)/adder_carry.vhdl \
+				  $(GENESIS)/dffnsre.vhdl \
+				  $(GENESIS)/dffsre.vhdl \
+				  $(GENESIS)/latchsre.vhdl \
+				  $(GENESIS)/lut.vhdl \
+				  $(GENESIS)/shr.vhdl \
+				  $(GENESIS2)/cells_sim.v \
+				  $(GENESIS2)/cells_sim.vhd \
+				  $(GENESIS2)/dsp_sim.v \
+				  $(GENESIS2)/brams_sim.v \
+				  $(GENESIS2)/ffs_map.v \
+				  $(GENESIS2)/dsp_map.v \
+				  $(GENESIS2)/dsp_final_map.v \
+				  $(GENESIS2)/arith_map.v \
+				  $(GENESIS2)/all_arith_map.v \
+				  $(GENESIS2)/brams_map.v \
+				  $(GENESIS2)/brams_map_new.v \
+				  $(GENESIS2)/brams_final_map.v \
+				  $(GENESIS2)/brams_final_map_new.v \
+				  $(GENESIS2)/brams.txt \
+				  $(GENESIS2)/brams_new.txt \
+				  $(GENESIS2)/brams_new_swap.txt \
+				  $(GENESIS2)/brams_async.txt \
+				  $(GENESIS2)/TDP18K_FIFO.v \
+				  $(GENESIS2)/sram1024x18.v \
+				  $(GENESIS2)/ufifo_ctl.v \
+				  $(GENESIS2)/cell_sim_blackbox.v \
+				  $(GENESIS3)/cells_sim.vhd \
+				  $(GENESIS3)/brams_sim.v \
+				  $(GENESIS3)/ffs_map.v \
+				  $(GENESIS3)/dsp_map.v \
+				  $(GENESIS3)/dsp_final_map.v \
+				  $(GENESIS3)/arith_map.v \
+				  $(GENESIS3)/all_arith_map.v \
+				  $(GENESIS3)/brams_map.v \
+				  $(GENESIS3)/brams_map_new.v \
+				  $(GENESIS3)/brams_final_map.v \
+				  $(GENESIS3)/brams_final_map_new.v \
+				  $(GENESIS3)/brams.txt \
+				  $(GENESIS3)/brams_new.txt \
+				  $(GENESIS3)/brams_new_swap.txt \
+				  $(GENESIS3)/brams_async.txt \
+				  $(GENESIS3)/TDP18K_FIFO.v \
+				  $(GENESIS3)/sram1024x18.v \
+				  $(GENESIS3)/ufifo_ctl.v \
+				  $(GENESIS3)/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v \
+				  $(GENESIS3)/llatches_sim.v \
+				  $(GENESIS3)/dsp38_map.v \
+				  $(GENESIS3)/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v
+
+NAME = pow-extract
+SOURCES = src/rs_pow_extract.cc 
+
+OBJS := $(SOURCES:cc=o)
+
+all: $(NAME).so
+
+$(OBJS): %.o: %.cc $(DEPS)
+	$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -c -o $@ $(filter %.cc, $^)
+
+$(NAME).so: $(OBJS)
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $^ $(LDLIBS)
+
+install_plugin: $(NAME).so
+	install -D $< $(PLUGINS_DIR)/$<
+
+install_modules: $(VERILOG_MODULES)
+	$(foreach f,$^,install -D $(f) $(DATA_DIR)/rapidsilicon/$(f);)
+
+.PHONY: install
+install: install_plugin install_modules
+
+valgrind_gen:
+	$(MAKE) -C tests valgrind_gen YOSYS_PATH=$(YOSYS_PATH)
+
+valgrind:
+	$(MAKE) -C tests valgrind_gen2 YOSYS_PATH=$(YOSYS_PATH)
+
+test_gen:
+	$(MAKE) -C tests tests_gen YOSYS_PATH=$(YOSYS_PATH)
+
+test:
+	$(MAKE) -C tests tests_gen2 YOSYS_PATH=$(YOSYS_PATH)
+
+clean:
+	rm -rf src/*.d src/*.o *.so pmgen/
+

pow_extract/README.md

@@ -0,0 +1,2 @@
+# pow-extract
+Rapidsilicon's Yosys Plugin