Merge pull request #524 from RapidSilicon/EDA-2377_fix

EDA-2377 Updated condition for read_first TDP for new_RS_BRAM PRIMITIVES
os-fpga · Jan 9, 2024 · b8004e7 · b8004e7
2 parents 6b4fdf2 + c4b1ebb
commit b8004e7
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Showing 5 changed files with 23 additions and 5 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -16,7 +16,7 @@ set(VERSION_MAJOR 0)
 set(VERSION_MINOR 0)
 
 
-set(VERSION_PATCH 267)
+set(VERSION_PATCH 268)
 
 
 project(yosys_verific_rs)

diff --git a/RTL_Benchmark b/RTL_Benchmark
diff --git a/suites/yosys_validation/bram_valid.json b/suites/yosys_validation/bram_valid.json
@@ -7,6 +7,12 @@
     "num_process": 4,
     "timeout": 1800,
     "benchmarks": {
+        "EDA-2292": {
+            "compile_status" : "active",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-2292/",
+            "top_module": "ram_simple_dp_dc_with_re_512x32"
+        },
         "EDA-1776": {
             "compile_status" : "active",
             "sim_status": "active",
@@ -182,7 +188,7 @@
             "top_module": "rams_sp_reg_addr_readmem_1024x1"
         },
         "EDA-1091": {
-            "compile_status" : "active",
+            "compile_status" : "inactive",
             "sim_status": "inactive",
             "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1091/",
             "top_module": "aes_256_sr_top"
@@ -318,6 +324,18 @@
             "sim_status": "inactive",
             "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1436",
             "top_module": "rams_sp_rf_rst_async_512x16_block"
+        },
+        "read_first_tdp_512x16": {
+            "compile_status" : "inactive",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/read_first_tdp_512x16/",
+            "top_module": "ram_true_dp_rf_512x16"
+        },
+        "read_first_tdp_if_if_512x16": {
+            "compile_status" : "inactive",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/read_first_tdp_if_if_512x16/",
+            "top_module": "read_first_tdp_if_if_512x16"
         }
     }
 }
diff --git a/yosys b/yosys
diff --git a/yosys-rs-plugin b/yosys-rs-plugin