Update README.

os-fpga · Mar 10, 2023 · c379f03 · c379f03
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diff --git a/README.md b/README.md
@@ -34,6 +34,7 @@ The repository has the following submodules:
  - [logic_synthesis-rs](https://github.com/RapidSilicon/logic_synthesis-rs.git) 
  - [RTL_Benchmark](https://github.com/RapidSilicon/RTL_Benchmark.git)
 
+The directory structure is the following:
 - `analyze` directory contains analyze tool and it's unit tests.
 - `benchmarks` directory contains benchmark open-source designs - SHOULD BE REMOVED:
   - `verilog` holds Verilog language desings.