Json file has been updated

os-fpga · Oct 13, 2023 · ed95ca6 · ed95ca6
1 parent 30f0030
commit ed95ca6
Showing 1 changed file with 80 additions and 0 deletions.
diff --git a/suites/Golden/Golden_synth_rs_ade_with_bram_with_dsp.json b/suites/Golden/Golden_synth_rs_ade_with_bram_with_dsp.json
@@ -21,6 +21,86 @@
             "name": "hypotenuse",
             "rtl_path": "RTL_Benchmark/Verilog/EPFL/hypotenuse/rtl",
             "top_module": "top"
+        },
+        {   
+            "name" : "add_output_of_four_multipliers", 
+            "rtl_path": "RTL_Benchmark/Verilog/yosys_validation/DSP_Designs/add_output_of_four_multipliers",
+            "top_module": "add_output_of_four_multipliers"
+        },
+        {
+            "name": "rc4-prbs",
+            "rtl_path": "RTL_Benchmark/Verilog/Cores/crypto_core/rc4-prbs/trunk",
+            "top_module": "rc4"
+        },
+        {
+            "name": "wrapper_KeyExpantion",
+            "rtl_path": "RTL_Benchmark/Verilog/ql_design/KeyExpantion/wrapper_rtl",
+            "top_module": "wrapper_KeyExpantion"
+        },
+        {
+            "name": "lsu",
+            "rtl_path": "RTL_Benchmark/SVerilog/Cores/Cores-SweRV-EL2/design/lsu",
+            "top_module": "el2_lsu"
+        },
+        {
+            "name": "twofish_128",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_128",
+            "top_module": "twofish_whit_keysched128"
+        },
+        {
+            "name": "twofish_256",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_256",
+            "top_module": "twofish_whit_keysched256"
+        },
+        {
+            "name": "twofish_192",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/twofish/trunk/vhdl/twofish_192",
+            "top_module": "twofish_whit_keysched192"
+        },
+        {
+            "name": "rsa",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/rsa/trunk/rtl/vhdl",
+            "top_module": "RSACypher"
+        },
+        {
+            "name": "b15",
+            "rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b15/rtl",
+            "top_module": "b15"
+        },
+        {
+            "name": "salsa20",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/salsa20/trunk/rtl",
+            "top_module": "salsaa"
+        },
+        {
+            "name": "threeasc_key_schedule",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/key_schedule/src",
+            "top_module": "key_schedule"
+        },
+        {
+            "name": "threeasc_aes_c_1",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/aes_c_1/src",
+            "top_module": "aes_fsm_enc"
+        },
+        {
+            "name": "b08",
+            "rtl_path": "RTL_Benchmark/VHDL/itc99-poli/itc99/b08/rtl",
+            "top_module": "b08"
+        },
+        {
+            "name": "threeasc_aes_c_3",
+            "rtl_path": "RTL_Benchmark/VHDL/Cores/crypto_core/threeaesc/rtl/aes_c_3/src",
+            "top_module": "aes_fsm_enc"
+        },
+        {
+            "name": "aes",
+            "rtl_path": "RTL_Benchmark/SVerilog/opentitan/ip/aes/rtl",
+            "top_module": "aes"
+        },
+        {
+            "name": "kmac",
+            "rtl_path": "RTL_Benchmark/SVerilog/opentitan/ip/kmac/rtl",
+            "top_module": "kmac"
         }
     ],
     "benchmarks": [