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@oscc-ip

OSCC IP Project

Develop and maintain IP Projects under OSCC (Open Source Chip Community).

OSCC IP: A series of Verified HDL IP with Accurate-cycle and Event-driven Model

Hi, OSCC IP Project 👋

OSCC IP Project contains a bundle of IPs which aim to improve development experience of processor and SoC design. Now it mainly focus on frontend and verification field. We hope it can be integrated by other components to build a common workflow for agile hardware development from frontend to backend one day.

Motivation

IPs list and development state:

  • SPC: SPEC complete
  • RTF: RTL frozen
  • SMT: SMOKE test
  • UVV: UVM verif
  • FUC: FUNCTION coverage
  • COC: CODE coverage
  • SOI: SoC integ
  • FPE: FPGA emu
  • TPT: TAPEOUT test
IP MILESTONE
archinfo
rng
sram
ps2
gpio
clint
crc
pwm
timer
wdg
rtc
uart
i2c
spi
vga
plic
rcu
i2s
sdram
psram
tapeout1
  1. this PRIVATE repo contains some tapeout-verified IPs:
    1. chiplink: a 8-bits D2D(die-to-die) bus interface derived from SiFive ChipLink.
    2. keyboard: an axi4-lite based ps2 keyboard IP.
    3. spi: an apb3-based standard SPI IP.
    4. uart: an apb3-based UART IP compatible with UART16550.
More Info

Template

Refer to the template repo. If you want to create a new ip repo, You need to:

  • Use this repository template to create a new repo
  • Update the content [IP NAME] in header file and remove the header file.

Style

refer to the style.md.

Contribution

If you want to contribute to this project, be sure to review the guidelines. This is an open project and contributions and collaborations are always welcome!! This project adheres to OSCC IP's code_of_conduct. By participating, you are expected to uphold this code.

we use GitHub issues for tracking requests and bugs, so please direct specific questions to issues panel.

The OSCC IP project strives to abide by generally accepted best practices in open-source software development, you can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄

License

All of the IPs codes are redistributed or released under the OSI Approved LICENSE MulanPSL2.

Acknowledgement

Reference

Pinned Loading

  1. sdram sdram Public

    An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

    Scala 14 2

  2. vga vga Public

    An AXI4-based VGA Controller

    SystemVerilog 3

  3. gpio gpio Public

    An APB4-based GPIO Controller

    SystemVerilog 1

  4. timer timer Public

    An APB4-based Timer Controller

    SystemVerilog 1

  5. common common Public

    A SystemVerilog Components Library

    SystemVerilog 2

  6. sram sram Public

    An AXI4-based SRAM Controller

    SystemVerilog 6

Repositories

Showing 10 of 25 repositories
  • psram Public

    An AXI4-based PSRAM Controller

    oscc-ip/psram’s past year of commit activity
    SystemVerilog 4 MulanPSL-2.0 0 0 0 Updated Oct 20, 2024
  • timer Public

    An APB4-based Timer Controller

    oscc-ip/timer’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Oct 18, 2024
  • common Public

    A SystemVerilog Components Library

    oscc-ip/common’s past year of commit activity
    SystemVerilog 2 MulanPSL-2.0 0 0 0 Updated Oct 18, 2024
  • rcu Public

    A Reset and Clock Unit

    oscc-ip/rcu’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Oct 18, 2024
  • sdram Public

    An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

    oscc-ip/sdram’s past year of commit activity
    Scala 14 2 0 0 Updated Oct 16, 2024
  • vga Public

    An AXI4-based VGA Controller

    oscc-ip/vga’s past year of commit activity
    SystemVerilog 3 MulanPSL-2.0 0 0 0 Updated Oct 16, 2024
  • rtc Public

    An APB4-based RTC Controller

    oscc-ip/rtc’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Oct 16, 2024
  • wdg Public

    An APB4-based WatchDog Controller

    oscc-ip/wdg’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Oct 16, 2024
  • pwm Public

    An APB4-based PWM Controller

    oscc-ip/pwm’s past year of commit activity
    SystemVerilog 1 MulanPSL-2.0 0 1 0 Updated Oct 16, 2024
  • spi Public

    An APB4-based SPI Controller

    oscc-ip/spi’s past year of commit activity
    SystemVerilog 2 MulanPSL-2.0 0 0 0 Updated Oct 14, 2024

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