Alpha 0.1

The current build ([email protected]) allows one to generate verilog testbench skeletons from a given verilog module file.

Constraints :

1. Can only parse 1 file at a time, containing only 1 module
2. Parses only a single type of code structure
3. Ignore bus widths
4. Parsing is done using greedy methods

Future releases will tackle the above constraints