Added a note about MSTATUS.FS update.

Signed-off-by: Pascal Gouedo <[email protected]>
pascalgouedo · Oct 19, 2023 · 34977aa · 34977aa
1 parent 3023e88
commit 34977aa
Showing 1 changed file with 13 additions and 5 deletions.
diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst
@@ -445,7 +445,7 @@ Detailed:
   +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
   | 30:15       | RO        | 0, Unimplemented.                                                                                                       |
   +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
-  | 14:13       | RW        | **FS:** Floating point State                                                                                            |
+  | 14:13       | RW        | **FS:** Floating point State (See note below)                                                                           |
   |             |           |                                                                                                                         |
   |             |           | 00 = Off                                                                                                                |
   |             |           |                                                                                                                         |
@@ -478,6 +478,10 @@ Detailed:
   | 2:0         | RO        | 0, Unimplemented.                                                                                                       |
   +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
 
+.. note::
+
+   As allowed by RISC-V ISA and to simplify MSTATUS.FS update in the design, the state is updated to Dirty when executing any F instructions except for all FSW ones.
+
 .. only:: USER
 
   User Status (``ustatus``)
@@ -652,8 +656,10 @@ Detailed:
   | 4:0         |   RW      | **Exception Code**   (See note below)                                            |
   +-------------+-----------+----------------------------------------------------------------------------------+
 
-**NOTE**: software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
-when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
+.. note::
+
+   Software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
+   when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
 
 
 Machine Trap Value (``mtval``)
@@ -1603,8 +1609,10 @@ Detailed:
   | 4:0         |   RW      | **Exception Code**   (See note below)                                              |
   +-------------+-----------+------------------------------------------------------------------------------------+
 
-  **NOTE**: software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR.  For example,
-  when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
+  .. note::
+
+   Software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
+   when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
 
 
 .. only:: PMP