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Merge pull request openhwgroup#842 from openhwgroup/dev
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Automatic PR dev->master
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@davideschiavone
davideschiavone authored Aug 3, 2023
2 parents b14f1ad + c02a42b commit ea8028f
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Showing 3 changed files with 48 additions and 23 deletions.
53 changes: 34 additions & 19 deletions rtl/cv32e40p_controller.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -223,6 +223,8 @@ module cv32e40p_controller import cv32e40p_pkg::*;
logic hwlp_end1_eq_pc;
logic hwlp_counter0_gt_1;
logic hwlp_counter1_gt_1;
logic hwlp_counter0_eq_1;
logic hwlp_counter1_eq_1;
logic hwlp_end0_eq_pc_plus4;
logic hwlp_end1_eq_pc_plus4;
logic hwlp_start0_leq_pc;
Expand Down Expand Up @@ -617,26 +619,34 @@ module cv32e40p_controller import cv32e40p_pkg::*;

// we can be at the end of HWloop due to a return from interrupt or ecall or ebreak or exceptions
if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
pc_mux_o = PC_HWLOOP;
if (~jump_done_q) begin
pc_set_o = 1'b1;
// Keep the instruction and the related address in the Aligner if
// ID is stalled during a jump
jump_done = 1'b1;
hwlp_dec_cnt_o[0] = 1'b1;
end
end
if(hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin
pc_mux_o = PC_HWLOOP;
if (~jump_done_q) begin
pc_set_o = 1'b1;
// Keep the instruction and the related address in the Aligner if
// ID is stalled during a jump
jump_done = 1'b1;
hwlp_dec_cnt_o[1] = 1'b1;
end
end
pc_mux_o = PC_HWLOOP;
if (~jump_done_q) begin
pc_set_o = 1'b1;
// Keep the instruction and the related address in the Aligner if
// ID is stalled during a jump
jump_done = 1'b1;
hwlp_dec_cnt_o[0] = 1'b1;
end
end
if (hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin
pc_mux_o = PC_HWLOOP;
if (~jump_done_q) begin
pc_set_o = 1'b1;
// Keep the instruction and the related address in the Aligner if
// ID is stalled during a jump
jump_done = 1'b1;
hwlp_dec_cnt_o[1] = 1'b1;
end
end
end

if (hwlp_end0_eq_pc && hwlp_counter0_eq_1) begin
hwlp_dec_cnt_o[0] = 1'b1;
end
if (hwlp_end1_eq_pc && hwlp_counter1_eq_1) begin
hwlp_dec_cnt_o[1] = 1'b1;
end

end

endcase // unique case (1'b1)
Expand Down Expand Up @@ -1269,6 +1279,8 @@ generate
assign hwlp_end1_eq_pc = hwlp_end_addr_i[1] == pc_id_i + 4; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i
assign hwlp_counter0_gt_1 = hwlp_counter_i[0] > 1;
assign hwlp_counter1_gt_1 = hwlp_counter_i[1] > 1;
assign hwlp_counter0_eq_1 = hwlp_counter_i[0] == 1;
assign hwlp_counter1_eq_1 = hwlp_counter_i[1] == 1;
assign hwlp_end0_eq_pc_plus4 = hwlp_end_addr_i[0] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[0] - 4 == pc_id_i + 4
assign hwlp_end1_eq_pc_plus4 = hwlp_end_addr_i[1] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i + 4
assign hwlp_start0_leq_pc = hwlp_start_addr_i[0] <= pc_id_i;
Expand All @@ -1285,6 +1297,8 @@ generate
assign hwlp_end1_eq_pc = 1'b0;
assign hwlp_counter0_gt_1 = 1'b0;
assign hwlp_counter1_gt_1 = 1'b0;
assign hwlp_counter0_eq_1 = 1'b0;
assign hwlp_counter1_eq_1 = 1'b0;
assign hwlp_end0_eq_pc_plus4 = 1'b0;
assign hwlp_end1_eq_pc_plus4 = 1'b0;
assign hwlp_start0_leq_pc = 1'b0;
Expand Down Expand Up @@ -1555,6 +1569,7 @@ endgenerate
(hwlp_start_addr_i == 'b0) && (hwlp_end_addr_i == 'b0) && (hwlp_counter_i[1] == 32'b0) && (hwlp_counter_i[0] == 32'b0) &&
(hwlp_dec_cnt_o == 2'b0) && (hwlp_jump_o == 1'b0) && (hwlp_targ_addr_o == 32'b0) &&
(hwlp_end0_eq_pc == 1'b0) && (hwlp_end1_eq_pc == 1'b0) && (hwlp_counter0_gt_1 == 1'b0) && (hwlp_counter1_gt_1 == 1'b0) &&
(hwlp_counter0_eq_1 == 1'b0) && (hwlp_counter1_eq_1 == 1'b0) &&
(hwlp_end0_eq_pc_plus4 == 1'b0) && (hwlp_end1_eq_pc_plus4 == 1'b0) && (hwlp_start0_leq_pc == 0) && (hwlp_start1_leq_pc == 0) &&
(hwlp_end0_geq_pc == 1'b0) && (hwlp_end1_geq_pc == 1'b0) && (hwlp_end_4_id_d == 1'b0) && (hwlp_end_4_id_q == 1'b0));
endproperty
Expand Down
7 changes: 6 additions & 1 deletion rtl/cv32e40p_cs_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -505,8 +505,13 @@ module cv32e40p_cs_registers
// marchid: Machine Architecture ID
CSR_MARCHID: csr_rdata_int = MARCHID;

// mimpid, Machine Implementation ID
CSR_MIMPID: begin
csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0;
end

// unimplemented, read 0 CSRs
CSR_MIMPID, CSR_MTVAL: csr_rdata_int = 'b0;
CSR_MTVAL: csr_rdata_int = 'b0;

CSR_TSELECT, CSR_TDATA3, CSR_MCONTEXT, CSR_SCONTEXT: csr_rdata_int = 'b0; // Always read 0
CSR_TDATA1: csr_rdata_int = tmatch_control_rdata;
Expand Down
11 changes: 8 additions & 3 deletions rtl/cv32e40p_id_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -808,7 +808,7 @@ module cv32e40p_id_stage
apu_read_regs[0] = regfile_addr_ra_id;
apu_read_regs_valid[0] = 1'b1;
end // OP_A_REGA_OR_FWD:
OP_A_REGB_OR_FWD: begin
OP_A_REGB_OR_FWD, OP_A_REGC_OR_FWD: begin
apu_read_regs[0] = regfile_addr_rb_id;
apu_read_regs_valid[0] = 1'b1;
end
Expand Down Expand Up @@ -847,8 +847,13 @@ module cv32e40p_id_stage
apu_read_regs_valid[2] = 1'b1;
end
OP_C_REGC_OR_FWD: begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b1;
if (alu_op_a_mux_sel != OP_A_REGC_OR_FWD) begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b1;
end else begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b0;
end
end
default: begin
apu_read_regs[2] = regfile_addr_rc_id;
Expand Down

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