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Merge pull request #44 from perlindgren/format_experiment
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Format experiment
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perlindgren authored Jul 27, 2023
2 parents 4ee302d + 4a7c9d3 commit 2accb4f
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Showing 45 changed files with 1,266 additions and 827 deletions.
1 change: 1 addition & 0 deletions .vscode/settings.json
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@
"hoverable",
"lightcoral",
"lightgray",
"lightgreen",
"menubutton",
"petgraph",
"println",
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8 changes: 8 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -2,6 +2,14 @@

Tracking changes per date:

## 230727

- `Signal` type now incorporates formatting. This allows the default formatting to be set on a signal on creation. The data and formatting can be read/written separately by setters/getters.

- Internal component fields are now `pub(crate)`. This allows internal component structure to be hidden outside the crate, thus examples and other users cannot affect the component state, also we are free to change internal repr without affecting examples/users (given that the API can remain stable).

- `rc_new` implemented for all components. (Examples updated.) We might want to change `new` to `_new` and `rc_new` to `new`.

## 230725

- Implemented the `ProbeAssert` component, that assert a set sequence of inputs. Made some updates so reading outside of the assert/stim buffers gives `Signal::Unknown` instead of panic (if not in test mode).
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20 changes: 14 additions & 6 deletions Cargo.toml
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Expand Up @@ -60,33 +60,41 @@ name = "component_tests"
required-features = ["components"]

[[example]]
name = "add"
name = "add_edit"
required-features = ["components"]

[[example]]
name = "add_mux"
required-features = ["components"]

[[example]]
name = "add_reg_compound_wire"
required-features = ["components"]

[[example]]
name = "add_reg"
required-features = ["components"]

[[example]]
name = "mux"
name = "add"
required-features = ["components"]

[[example]]
name = "data_mem"
required-features = ["components"]

[[example]]
name = "reg"
name = "mux_edit"
required-features = ["components"]

[[example]]
name = "sext"
name = "probe_edit"
required-features = ["components"]

[[example]]
name = "data_mem"
name = "probe_stim_assert"
required-features = ["components"]

[[example]]
name = "add_reg_compound_wire"
name = "sext"
required-features = ["components"]
51 changes: 23 additions & 28 deletions examples/add.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use std::{path::PathBuf, rc::Rc};
use std::path::PathBuf;
use syncrim::{
common::{ComponentStore, Input},
components::*,
Expand All @@ -9,35 +9,30 @@ fn main() {
fern_setup();
let cs = ComponentStore {
store: vec![
Rc::new(Add {
id: "add".to_string(),
pos: (200.0, 120.0),
a_in: Input::new("c1", "out"),

b_in: Input::new("c2", "out"),
}),
Add::rc_new(
"add",
(200.0, 120.0),
Input::new("c1", "out"),
Input::new("c2", "out"),
),
Constant::rc_new("c1", (60.0, 100.0), 3),
Constant::rc_new("c2", (60.0, 140.0), 4),
Rc::new(Wire {
id: "w1".to_string(),
pos: vec![(110.0, 100.0), (180.0, 100.0)],
input: Input::new("c1", "out"),
}),
Rc::new(Wire {
id: "w2".to_string(),
pos: vec![(110.0, 140.0), (180.0, 140.0)],
input: Input::new("c2", "out"),
}),
Rc::new(Wire {
id: "w3".to_string(),
pos: vec![(220.0, 120.0), (260.0, 120.0)],
input: Input::new("add", "out"),
}),
Rc::new(Probe {
id: "p1".to_string(),
pos: (270.0, 120.0),
input: Input::new("add", "out"),
}),
Wire::rc_new(
"w1",
vec![(110.0, 100.0), (180.0, 100.0)],
Input::new("c1", "out"),
),
Wire::rc_new(
"w2",
vec![(110.0, 140.0), (180.0, 140.0)],
Input::new("c2", "out"),
),
Wire::rc_new(
"w3",
vec![(220.0, 120.0), (260.0, 120.0)],
Input::new("add", "out"),
),
Probe::rc_new("p1", (270.0, 120.0), Input::new("add", "out")),
],
};

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55 changes: 25 additions & 30 deletions examples/add_edit.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use std::{path::PathBuf, rc::Rc};
use std::path::PathBuf;
use syncrim::{
common::{ComponentStore, Input},
components::*,
Expand All @@ -9,35 +9,30 @@ fn main() {
fern_setup();
let cs = ComponentStore {
store: vec![
Rc::new(Add {
id: "add".to_string(),
pos: (200.0, 120.0),
a_in: Input::new("c1", "out"),

b_in: Input::new("c2", "out"),
}),
Rc::new(ProbeEdit::new("c1", (60.0, 100.0))),
Rc::new(ProbeEdit::new("c2", (60.0, 140.0))),
Rc::new(Wire {
id: "w1".to_string(),
pos: vec![(110.0, 100.0), (180.0, 100.0)],
input: Input::new("c1", "out"),
}),
Rc::new(Wire {
id: "w2".to_string(),
pos: vec![(110.0, 140.0), (180.0, 140.0)],
input: Input::new("c2", "out"),
}),
Rc::new(Wire {
id: "w3".to_string(),
pos: vec![(220.0, 120.0), (260.0, 120.0)],
input: Input::new("add", "out"),
}),
Rc::new(Probe {
id: "p1".to_string(),
pos: (270.0, 120.0),
input: Input::new("add", "out"),
}),
Add::rc_new(
"add",
(200.0, 120.0),
Input::new("c1", "out"),
Input::new("c2", "out"),
),
ProbeEdit::rc_new("c1", (60.0, 100.0)),
ProbeEdit::rc_new("c2", (60.0, 140.0)),
Wire::rc_new(
"w1",
vec![(110.0, 100.0), (180.0, 100.0)],
Input::new("c1", "out"),
),
Wire::rc_new(
"w2",
vec![(110.0, 140.0), (180.0, 140.0)],
Input::new("c2", "out"),
),
Wire::rc_new(
"w3",
vec![(220.0, 120.0), (260.0, 120.0)],
Input::new("add", "out"),
),
Probe::rc_new("p1", (270.0, 120.0), Input::new("add", "out")),
],
};

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