Merge with master and fix riscv

.github/workflows/rust.yml

@@ -32,3 +32,12 @@ jobs:
           args: --no-default-features --features gui-egui
       - name: Run tests
         run: cargo test --workspace --no-default-features --features components --verbose
+  rustfmt:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+
+      - uses: Swatinem/rust-cache@v2
+
+      - name: rustfmt
+        run: cargo fmt --all -- --check

.gitignore

@@ -20,4 +20,11 @@ Cargo.lock
 *.gv
 
 # output.log generated by fern 
-output.log
+output.log
+
+riscv/*.o
+riscv/output
+
+riscv/riscv_asm/target/
+riscv/riscv_asm/memory.x
+riscv/riscv_asm/asm.s

.vscode/settings.json

@@ -11,6 +11,7 @@
     "Insr",
     "Keymap",
     "Luleå",
+    "Swatinem",
     "Textbox",
     "Tpdf",
     "blueviolet",
@@ -20,14 +21,18 @@
     "epaint",
     "graphviz",
     "hoverable",
+    "librust",
+    "lightcoral",
     "lightgray",
+    "lightgreen",
     "menubutton",
     "petgraph",
     "println",
     "regfile",
     "repr",
     "rgbaf",
     "rgbf",
+    "riscv",
     "rustfmt",
     "serde",
     "stim",
@@ -41,9 +46,12 @@
     "vizia",
     "winit",
     "xffff"
-  ]
+  ],
+  "[rust]": {
+    "editor.defaultFormatter": "rust-lang.rust-analyzer",
+    "editor.formatOnSave": true
+  }
   //,
-
   // "rust-analyzer.cargo.unsetTest": [
   //   "syncrim"
   // ],

CHANGELOG.md

@@ -2,8 +2,32 @@
 
 Tracking changes per date:
 
+## 230801
+
+- Simulator run/halt is implemented in `vizia` using a simple eventing mechanism. Later we might want to spawn a simulation thread for faster execution (right now its tied to frame rate).
+
+## 230731
+
+- Return type from `clock` (`fn clock(&self, _simulator: &mut Simulator) -> Result<(), Condition`).
+
+- RISC-V cross compilation.
+
+## 230727
+
+- `Signal` type now incorporates formatting. This allows the default formatting to be set on a signal on creation. The data and formatting can be read/written separately by setters/getters.
+
+- Internal component fields are now `pub(crate)`. This allows internal component structure to be hidden outside the crate, thus examples and other users cannot affect the component state, also we are free to change internal repr without affecting examples/users (given that the API can remain stable).
+
+- `rc_new` implemented for all components. (Examples updated.) We might want to change `new` to `_new` and `rc_new` to `new`.
+
 ## 230725
 
+- Added RISC-V components and model
+
+- Implemented the `ProbeAssert` component, that assert a set sequence of inputs. Made some updates so reading outside of the assert/stim buffers gives `Signal::Unknown` instead of panic (if not in test mode).
+
+  Asserts are run only in test mode, allowing gui testing to be more robust.
+
 - Refactored, `clock` as `cycle` and put it in the `Simulator` (thanks to Fredrik for suggesting this a while back). Now the Simulator holds the complete state, which is better.
 
 - Implemented the `ProbeStim` component, to provide a set sequence of outputs.

Cargo.toml

@@ -6,7 +6,7 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [workspace]
-members = ["mips"]
+members = ["mips", "riscv"]
 
 [dependencies]
 anyhow = "1.0.72"
@@ -60,33 +60,41 @@ name = "component_tests"
 required-features = ["components"]
 
 [[example]]
-name = "add"
+name = "add_edit"
 required-features = ["components"]
 
 [[example]]
 name = "add_mux"
 required-features = ["components"]
 
+[[example]]
+name = "add_reg_compound_wire"
+required-features = ["components"]
+
 [[example]]
 name = "add_reg"
 required-features = ["components"]
 
 [[example]]
-name = "mux"
+name = "add"
+required-features = ["components"]
+
+[[example]]
+name = "data_mem"
 required-features = ["components"]
 
 [[example]]
-name = "reg"
+name = "mux_edit"
 required-features = ["components"]
 
 [[example]]
-name = "sext"
+name = "probe_edit"
 required-features = ["components"]
 
 [[example]]
-name = "data_mem"
+name = "probe_stim_assert"
 required-features = ["components"]
 
 [[example]]
-name = "add_reg_compound_wire"
+name = "sext"
 required-features = ["components"]

GITHUB.md

@@ -1,6 +1,9 @@
 # Github workflow breakdown
-The workflow starts with checking out the repo, installing the required dependencies (`librust-atk-dev`, `librust-gdk-dev`, the Rust toolchain, and the Mold linker). It then restores the cache stored by `Swatinem/rust-cache@v2`. This includes the `~/.cargo` and `./target` directories, which contain installed binaries, the cargo registry, the cache, git dependencies and build artifacts of dependencies. 
+
+The workflow starts with checking out the repo, installing the required dependencies (`librust-atk-dev`, `librust-gdk-dev`, the Rust toolchain, and the Mold linker). It then restores the cache stored by `Swatinem/rust-cache@v2`. This includes the `~/.cargo` and `./target` directories, which contain installed binaries, the cargo registry, the cache, git dependencies and build artifacts of dependencies.
 
 Next, a build check is ran via `cargo build --verbose`, followed by clippy checks on the `gui-vizia` and `gui-egui` versions of the crate, and finally, the tests are ran via `cargo test --workspace --no-default-features --features components --verbose`.
 
 As a final step, the `Swatinem/rust-cache@v2` workflow updates the aforementioned cache for re-use by the next job.
+
+In parallel, a rustfmt check is ran via ``cargo fmt --all --check``. This ensures that all of the Rust code is formatted with ``cargo fmt``.

examples/add.rs

@@ -1,4 +1,4 @@
-use std::{path::PathBuf, rc::Rc};
+use std::path::PathBuf;
 use syncrim::{
     common::{ComponentStore, Input},
     components::*,
@@ -9,35 +9,30 @@ fn main() {
     fern_setup();
     let cs = ComponentStore {
         store: vec![
-            Rc::new(Add {
-                id: "add".to_string(),
-                pos: (200.0, 120.0),
-                a_in: Input::new("c1", "out"),
-
-                b_in: Input::new("c2", "out"),
-            }),
+            Add::rc_new(
+                "add",
+                (200.0, 120.0),
+                Input::new("c1", "out"),
+                Input::new("c2", "out"),
+            ),
             Constant::rc_new("c1", (60.0, 100.0), 3),
             Constant::rc_new("c2", (60.0, 140.0), 4),
-            Rc::new(Wire {
-                id: "w1".to_string(),
-                pos: vec![(110.0, 100.0), (180.0, 100.0)],
-                input: Input::new("c1", "out"),
-            }),
-            Rc::new(Wire {
-                id: "w2".to_string(),
-                pos: vec![(110.0, 140.0), (180.0, 140.0)],
-                input: Input::new("c2", "out"),
-            }),
-            Rc::new(Wire {
-                id: "w3".to_string(),
-                pos: vec![(220.0, 120.0), (260.0, 120.0)],
-                input: Input::new("add", "out"),
-            }),
-            Rc::new(Probe {
-                id: "p1".to_string(),
-                pos: (270.0, 120.0),
-                input: Input::new("add", "out"),
-            }),
+            Wire::rc_new(
+                "w1",
+                vec![(110.0, 100.0), (180.0, 100.0)],
+                Input::new("c1", "out"),
+            ),
+            Wire::rc_new(
+                "w2",
+                vec![(110.0, 140.0), (180.0, 140.0)],
+                Input::new("c2", "out"),
+            ),
+            Wire::rc_new(
+                "w3",
+                vec![(220.0, 120.0), (260.0, 120.0)],
+                Input::new("add", "out"),
+            ),
+            Probe::rc_new("p1", (270.0, 120.0), Input::new("add", "out")),
         ],
     };
 

examples/add_edit.rs

@@ -1,4 +1,4 @@
-use std::{path::PathBuf, rc::Rc};
+use std::path::PathBuf;
 use syncrim::{
     common::{ComponentStore, Input},
     components::*,
@@ -9,35 +9,30 @@ fn main() {
     fern_setup();
     let cs = ComponentStore {
         store: vec![
-            Rc::new(Add {
-                id: "add".to_string(),
-                pos: (200.0, 120.0),
-                a_in: Input::new("c1", "out"),
-
-                b_in: Input::new("c2", "out"),
-            }),
-            Rc::new(ProbeEdit::new("c1", (60.0, 100.0))),
-            Rc::new(ProbeEdit::new("c2", (60.0, 140.0))),
-            Rc::new(Wire {
-                id: "w1".to_string(),
-                pos: vec![(110.0, 100.0), (180.0, 100.0)],
-                input: Input::new("c1", "out"),
-            }),
-            Rc::new(Wire {
-                id: "w2".to_string(),
-                pos: vec![(110.0, 140.0), (180.0, 140.0)],
-                input: Input::new("c2", "out"),
-            }),
-            Rc::new(Wire {
-                id: "w3".to_string(),
-                pos: vec![(220.0, 120.0), (260.0, 120.0)],
-                input: Input::new("add", "out"),
-            }),
-            Rc::new(Probe {
-                id: "p1".to_string(),
-                pos: (270.0, 120.0),
-                input: Input::new("add", "out"),
-            }),
+            Add::rc_new(
+                "add",
+                (200.0, 120.0),
+                Input::new("c1", "out"),
+                Input::new("c2", "out"),
+            ),
+            ProbeEdit::rc_new("c1", (60.0, 100.0)),
+            ProbeEdit::rc_new("c2", (60.0, 140.0)),
+            Wire::rc_new(
+                "w1",
+                vec![(110.0, 100.0), (180.0, 100.0)],
+                Input::new("c1", "out"),
+            ),
+            Wire::rc_new(
+                "w2",
+                vec![(110.0, 140.0), (180.0, 140.0)],
+                Input::new("c2", "out"),
+            ),
+            Wire::rc_new(
+                "w3",
+                vec![(220.0, 120.0), (260.0, 120.0)],
+                Input::new("add", "out"),
+            ),
+            Probe::rc_new("p1", (270.0, 120.0), Input::new("add", "out")),
         ],
     };