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some risc-v components implemented for egui
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@onsdagens
onsdagens committed Oct 10, 2023
1 parent 6ca851b commit 868b3e5
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Showing 9 changed files with 501 additions and 33 deletions.
47 changes: 34 additions & 13 deletions riscv/examples/empty.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,22 +21,43 @@ struct Args {

fn main() {
let cs = ComponentStore { store: vec![] };
let dummy = Input::new("id", "field");
let lib = ComponentStore {
store: vec![Rc::new(InstrMem {
id: "dummy_instr_mem".to_string(),
pos: (0.0, 0.0),
pc: dummy.clone(),
bytes: BTreeMap::new(),
})],
};
#[cfg(feature = "gui-egui")]
let _library = syncrim::gui_egui::editor::Library(lib.store);
let path = PathBuf::from("riscv.json");
cs.save_file(&path);

let dummy = Input::new("id", "field");
#[cfg(feature = "gui-egui")]
syncrim::gui_egui::gui(cs, &path, syncrim::gui_egui::editor::Library::default()).ok();
{
let lib = ComponentStore {
store: vec![
Rc::new(InstrMem {
width: INSTR_MEM_WIDTH,
height: INSTR_MEM_HEIGHT,
id: "dummy_instr_mem".to_string(),
pos: (0.0, 0.0),
pc: dummy.clone(),
bytes: BTreeMap::new(),
}),
Rc::new(ALU {
id: "dummy_alu".to_string(),
pos: (0.0, 0.0),
operator_i: dummy.clone(),
operand_a_i: dummy.clone(),
operand_b_i: dummy.clone(),
}),
Rc::new(BranchLogic {
width: BRANCH_LOGIC_WIDTH,
height: BRANCH_LOGIC_HEIGHT,
id: "dummy_blu".to_string(),
pos: (0.0, 0.0),
rs1: dummy.clone(),
rs2: dummy.clone(),
ctrl: dummy.clone(),
enable: dummy.clone(),
}),
],
};
let library = syncrim::gui_egui::editor::Library(lib.store);
syncrim::gui_egui::gui(cs, &path, syncrim::gui_egui::editor::Library(library.0)).ok();
}

#[cfg(feature = "gui-vizia")]
syncrim::gui_vizia::gui(cs, &path);
Expand Down
4 changes: 4 additions & 0 deletions riscv/examples/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,8 @@ fn main() {
Input::new("jalr_se", "out"),
),
Rc::new(BranchLogic {
width: 60.0,
height: 60.0,
id: "branch_logic".to_string(),
pos: (725.0, 300.0),
rs1: Input::new("reg_file", "reg_a"),
Expand Down Expand Up @@ -138,6 +140,8 @@ fn main() {
32,
),
Rc::new(InstrMem {
width: 200.0,
height: 100.0,
id: "instr_mem".to_string(),
pos: (180.0, 400.0),
pc: Input::new("reg", "out"),
Expand Down
27 changes: 26 additions & 1 deletion riscv/src/components/alu.rs
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Original file line number Diff line number Diff line change
@@ -1,7 +1,13 @@
use log::trace;
use serde::{Deserialize, Serialize};
#[cfg(feature = "gui-egui")]
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::{
common::{Component, Condition, Input, InputPort, OutputType, Ports, SignalValue, Simulator},
common::{
Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
},
signal::SignalSigned,
};

Expand All @@ -27,6 +33,25 @@ impl Component for ALU {
fn to_(&self) {
println!("ALU");
}
#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy = Input::new("dummy", "out");
Box::new(Rc::new(ALU {
id: id.to_string(),
pos: (pos.0, pos.1),
operator_i: dummy.clone(),
operand_a_i: dummy.clone(),
operand_b_i: dummy.clone(),
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
ALU_OPERAND_A_I_ID => self.operand_a_i = new_input,
ALU_OPERAND_B_I_ID => self.operand_b_i = new_input,
ALU_OPERATOR_I_ID => self.operator_i = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down
50 changes: 49 additions & 1 deletion riscv/src/components/branch_logic.rs
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Original file line number Diff line number Diff line change
@@ -1,7 +1,11 @@
use log::trace;
use serde::{Deserialize, Serialize};
#[cfg(feature = "gui-egui")]
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::common::{
Component, Condition, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator,
};

pub const BRANCH_LOGIC_RS1_ID: &str = "rs1";
Expand All @@ -11,8 +15,13 @@ pub const BRANCH_LOGIC_ENABLE_ID: &str = "enable";

pub const BRANCH_LOGIC_OUT_ID: &str = "out";

pub const BRANCH_LOGIC_HEIGHT: f32 = 60.0;
pub const BRANCH_LOGIC_WIDTH: f32 = 60.0;

#[derive(Serialize, Deserialize)]
pub struct BranchLogic {
pub width: f32,
pub height: f32,
pub id: String,
pub pos: (f32, f32),

Expand All @@ -28,6 +37,29 @@ impl Component for BranchLogic {
fn to_(&self) {
println!("BranchLogic");
}
#[cfg(feature = "gui-egui")]
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy = Input::new("dummy", "out");
Box::new(Rc::new(BranchLogic {
width: 60.0,
height: 60.0,
id: id.to_string(),
pos: (pos.0, pos.1),
rs1: dummy.clone(),
rs2: dummy.clone(),
ctrl: dummy.clone(),
enable: dummy.clone(),
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
BRANCH_LOGIC_RS1_ID => self.rs1 = new_input,
BRANCH_LOGIC_RS2_ID => self.rs2 = new_input,
BRANCH_LOGIC_CTRL_ID => self.ctrl = new_input,
BRANCH_LOGIC_ENABLE_ID => self.enable = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down Expand Up @@ -176,6 +208,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -231,6 +265,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -286,6 +322,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -348,6 +386,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -410,6 +450,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -472,6 +514,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -541,6 +585,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down Expand Up @@ -580,6 +626,8 @@ mod test {
Rc::new(ProbeOut::new("ctrl")),
Rc::new(ProbeOut::new("enable")),
Rc::new(BranchLogic {
width: 0.0,
height: 0.0,
id: "blu".to_string(),
pos: (0.0, 0.0),
rs1: Input::new("rs1", "out"),
Expand Down
17 changes: 16 additions & 1 deletion riscv/src/components/instr_mem.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,18 @@ use serde::{Deserialize, Serialize};
use std::rc::Rc;
#[cfg(feature = "gui-egui")]
use syncrim::common::EguiComponent;
use syncrim::common::{Component, Condition, Input, InputPort, OutputType, Ports, Simulator};
use syncrim::common::{Component, Condition, Id, Input, InputPort, OutputType, Ports, Simulator};
pub const INSTR_MEM_PC_ID: &str = "pc";

pub const INSTR_MEM_INSTRUCTION_ID: &str = "instruction";

pub const INSTR_MEM_HEIGHT: f32 = 100.0;
pub const INSTR_MEM_WIDTH: f32 = 200.0;

#[derive(Serialize, Deserialize, Clone)]
pub struct InstrMem {
pub width: f32,
pub height: f32,
pub id: String,
pub pos: (f32, f32),
pub bytes: BTreeMap<usize, u8>,
Expand All @@ -29,12 +34,20 @@ impl Component for InstrMem {
fn dummy(&self, id: &str, pos: (f32, f32)) -> Box<Rc<dyn EguiComponent>> {
let dummy_input = Input::new("dummy", "out");
Box::new(Rc::new(InstrMem {
width: INSTR_MEM_WIDTH,
height: INSTR_MEM_HEIGHT,
id: id.to_string(),
pos: (pos.0, pos.1),
bytes: BTreeMap::new(),
pc: dummy_input,
}))
}
fn set_id_port(&mut self, target_port_id: Id, new_input: Input) {
match target_port_id.as_str() {
INSTR_MEM_PC_ID => self.pc = new_input,
_ => (),
}
}
fn get_id_ports(&self) -> (String, Ports) {
(
self.id.clone(),
Expand Down Expand Up @@ -92,6 +105,8 @@ mod test {
store: vec![
Rc::new(ProbeOut::new("pc")),
Rc::new(InstrMem {
width: 0.0,
height: 0.0,
id: "imem".to_string(),
pos: (0.0, 0.0),
pc: Input::new("pc", "out"),
Expand Down
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