Merge pull request #58 from perlindgren/simulation_status

Return type

.vscode/settings.json

@@ -11,6 +11,7 @@
     "Insr",
     "Keymap",
     "Luleå",
+    "Swatinem",
     "Textbox",
     "Tpdf",
     "blueviolet",
@@ -20,6 +21,7 @@
     "epaint",
     "graphviz",
     "hoverable",
+    "librust",
     "lightcoral",
     "lightgray",
     "lightgreen",

CHANGELOG.md

@@ -4,6 +4,8 @@ Tracking changes per date:
 
 ## 230731
 
+- Return type from `clock` (`fn clock(&self, _simulator: &mut Simulator) -> Result<(), Condition`).
+
 - RISC-V cross compilation.
 
 ## 230727

GITHUB.md

@@ -1,5 +1,6 @@
 # Github workflow breakdown
-The workflow starts with checking out the repo, installing the required dependencies (`librust-atk-dev`, `librust-gdk-dev`, the Rust toolchain, and the Mold linker). It then restores the cache stored by `Swatinem/rust-cache@v2`. This includes the `~/.cargo` and `./target` directories, which contain installed binaries, the cargo registry, the cache, git dependencies and build artifacts of dependencies. 
+
+The workflow starts with checking out the repo, installing the required dependencies (`librust-atk-dev`, `librust-gdk-dev`, the Rust toolchain, and the Mold linker). It then restores the cache stored by `Swatinem/rust-cache@v2`. This includes the `~/.cargo` and `./target` directories, which contain installed binaries, the cargo registry, the cache, git dependencies and build artifacts of dependencies.
 
 Next, a build check is ran via `cargo build --verbose`, followed by clippy checks on the `gui-vizia` and `gui-egui` versions of the crate, and finally, the tests are ran via `cargo test --workspace --no-default-features --features components --verbose`.
 

mips/src/components/instr_mem.rs

@@ -1,7 +1,7 @@
 use serde::{Deserialize, Serialize};
 use std::rc::Rc;
 use syncrim::common::{
-    Component, Input, OutputType, Ports, SignalUnsigned, SignalValue, Simulator,
+    Component, Condition, Input, OutputType, Ports, SignalUnsigned, SignalValue, Simulator,
 };
 
 #[derive(Serialize, Deserialize)]
@@ -31,7 +31,7 @@ impl Component for InstrMem {
         )
     }
 
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         let instr: SignalValue =
             match TryInto::<SignalUnsigned>::try_into(simulator.get_input_value(&self.pc)) {
                 Ok(pc) => {
@@ -48,6 +48,7 @@ impl Component for InstrMem {
         // set output
         trace!("--- output {:?}", instr);
         simulator.set_out_value(&self.id, "out", instr);
+        Ok(())
     }
 }
 

mips/src/components/reg_file.rs

@@ -3,7 +3,7 @@ use num_enum::TryFromPrimitive;
 use serde::{Deserialize, Serialize};
 use std::ops::{Deref, Range};
 use std::{cell::RefCell, rc::Rc};
-use syncrim::common::{Component, Input, OutputType, Ports, SignalUnsigned, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, SignalUnsigned, Simulator};
 
 #[allow(non_camel_case_types)]
 #[rustfmt::skip]
@@ -215,7 +215,7 @@ impl Component for RegFile {
         )
     }
 
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         if simulator.get_input_value(&self.write_enable) == (true as SignalUnsigned).into() {
             let data = simulator.get_input_value(&self.write_data);
             trace!("data {:?}", data);
@@ -235,6 +235,7 @@ impl Component for RegFile {
         let reg_value_b = self.read_reg(simulator, &self.read_addr2);
         trace!("reg_value {}", reg_value_b);
         simulator.set_out_value(&self.id, "reg_b", reg_value_b);
+        Ok(())
     }
 }
 

riscv/README.md

@@ -1,4 +1,5 @@
 # RISCV
+
 RISCV specific components.
 
 ```cargo run --example riscv```

riscv/src/components/alu.rs

@@ -1,7 +1,7 @@
 use log::trace;
 use serde::{Deserialize, Serialize};
 use syncrim::{
-    common::{Component, Input, OutputType, Ports, SignalValue, Simulator},
+    common::{Component, Condition, Input, OutputType, Ports, SignalValue, Simulator},
     signal::SignalSigned,
 };
 
@@ -41,15 +41,14 @@ impl Component for ALU {
         )
     }
     #[allow(non_snake_case)]
-    fn clock(&self, simulator: &mut Simulator) {
-        let operator_i: u32;
-        match simulator.get_input_value(&self.operator_i) {
-            SignalValue::Data(data) => operator_i = data,
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
+        let operator_i = match simulator.get_input_value(&self.operator_i) {
+            SignalValue::Data(data) => data,
             _ => {
                 simulator.set_out_value(&self.id, "result_o", SignalValue::Unknown);
-                return;
+                return Ok(());
             }
-        }
+        };
         //if i is set, these two must be set or panic is reasonable.
         let operand_a_i: u32 = simulator
             .get_input_value(&self.operand_a_i)
@@ -130,6 +129,7 @@ impl Component for ALU {
         }
         trace!("ALU result_o:{}", result_o);
         simulator.set_out_value(&self.id, "result_o", result_o);
+        Ok(())
     }
 }
 #[cfg(test)]

riscv/src/components/branch_logic.rs

@@ -1,6 +1,6 @@
 use log::trace;
 use serde::{Deserialize, Serialize};
-use syncrim::common::{Component, Input, OutputType, Ports, SignalValue, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, SignalValue, Simulator};
 
 #[derive(Serialize, Deserialize)]
 pub struct BranchLogic {
@@ -35,7 +35,7 @@ impl Component for BranchLogic {
         )
     }
     #[allow(non_snake_case)]
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         let enable: u32 = simulator.get_input_value(&self.enable).try_into().unwrap();
         let out: SignalValue;
         let rs1: SignalValue = simulator.get_input_value(&self.rs1);
@@ -133,6 +133,7 @@ impl Component for BranchLogic {
         }
         trace!("BranchLogic Out:{:?}", out);
         simulator.set_out_value(&self.id, "out", out);
+        Ok(())
     }
 }
 #[cfg(test)]

riscv/src/components/clic.rs

@@ -1,4 +1,4 @@
-use crate::common::{Component, Id, Input, OutputType, Ports, Signal, Simulator};
+use crate::common::{Component, Condition, Id, Input, OutputType, Ports, Signal, Simulator};
 use num_enum::IntoPrimitive;
 use num_enum::TryFromPrimitive;
 use serde::{Deserialize, Serialize};
@@ -183,7 +183,9 @@ impl Component for Mem {
         println!("Mem");
     }
 
-    fn to_string(&self)->String{"".to_string()}
+    fn to_string(&self) -> String {
+        "".to_string()
+    }
     fn get_id_ports(&self) -> (Id, Ports) {
         (
             self.id.clone(),

riscv/src/components/csr.rs

@@ -1,7 +1,7 @@
 use std::{cell::RefCell, collections::HashMap};
 
 use serde::{Deserialize, Serialize};
-use syncrim::common::{Component, Input, OutputType, Ports, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, Simulator};
 
 #[derive(Serialize, Deserialize)]
 pub struct CSR {
@@ -72,9 +72,10 @@ impl Component for CSR {
         )
     }
 
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         // get instr at pc/4
         let _we = simulator.get_input_value(&self.we);
+        Ok(())
 
         //simulator.set_out_val(&self.id, "instruction", we);
     }

riscv/src/components/decoder.rs

@@ -1,6 +1,6 @@
 use log::trace;
 use serde::{Deserialize, Serialize};
-use syncrim::common::{Component, Input, OutputType, Ports, SignalValue, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, SignalValue, Simulator};
 use syncrim::components::MemCtrl;
 
 #[derive(Serialize, Deserialize)]
@@ -50,7 +50,7 @@ impl Component for Decoder {
         )
     }
     #[allow(non_snake_case)]
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         let instruction: u32 = simulator
             .get_input_value(&self.instruction)
             .try_into()
@@ -440,6 +440,7 @@ impl Component for Decoder {
         simulator.set_out_value(&self.id, "branch_logic_ctl", branch_logic_ctl);
         simulator.set_out_value(&self.id, "branch_logic_enable", branch_logic_enable);
         simulator.set_out_value(&self.id, "jalr_imm", jalr_imm);
+        Ok(())
     }
 }
 

riscv/src/components/instr_mem.rs

@@ -2,7 +2,7 @@ use std::collections::BTreeMap;
 
 use log::trace;
 use serde::{Deserialize, Serialize};
-use syncrim::common::{Component, Input, OutputType, Ports, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, Simulator};
 
 #[derive(Serialize, Deserialize)]
 pub struct InstrMem {
@@ -28,7 +28,7 @@ impl Component for InstrMem {
         )
     }
 
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         // get instr at pc/4
         let pc: u32 = simulator.get_input_value(&self.pc).try_into().unwrap();
 
@@ -40,6 +40,7 @@ impl Component for InstrMem {
         trace!("pc:0x{:08x}", pc);
         // set output
         simulator.set_out_value(&self.id, "instruction", instr);
+        Ok(())
     }
 }
 mod test {

riscv/src/components/lsb_zero.rs

@@ -1,6 +1,6 @@
 use serde::{Deserialize, Serialize};
 use syncrim::{
-    common::{Component, Input, OutputType, Ports, Simulator},
+    common::{Component, Condition, Input, OutputType, Ports, Simulator},
     signal::SignalValue,
 };
 
@@ -28,7 +28,7 @@ impl Component for LSBZero {
         )
     }
     #[allow(non_snake_case)]
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         match simulator.get_input_value(&self.data_i) {
             SignalValue::Data(mut data) => {
                 let mask: u32 = !0b1;
@@ -37,6 +37,7 @@ impl Component for LSBZero {
             }
             _ => simulator.set_out_value(&self.id, "out", SignalValue::Unknown),
         }
+        Ok(())
     }
 }
 

riscv/src/components/reg_file.rs

@@ -3,7 +3,7 @@ use num_enum::TryFromPrimitive;
 use serde::{Deserialize, Serialize};
 use std::ops::{Deref, Range};
 use std::{cell::RefCell, rc::Rc};
-use syncrim::common::{Component, Input, OutputType, Ports, SignalUnsigned, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, SignalUnsigned, Simulator};
 use syncrim::signal::SignalValue;
 
 #[allow(non_camel_case_types)]
@@ -129,13 +129,13 @@ impl RegFile {
             SignalValue::Data(read_addr) => {
                 if read_addr > 0 {
                     trace!("read_addr {}", read_addr);
-                    return SignalValue::from(self.registers.borrow()[read_addr as usize]);
+                    SignalValue::from(self.registers.borrow()[read_addr as usize])
                 } else {
                     trace!("read_addr {}", read_addr);
-                    return SignalValue::from(0);
+                    SignalValue::from(0)
                 }
             }
-            _ => return SignalValue::Unknown,
+            _ => SignalValue::Unknown,
         }
     }
 }
@@ -157,7 +157,7 @@ impl Component for RegFile {
         )
     }
 
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         if simulator.get_input_value(&self.write_enable) == (true as SignalUnsigned).into() {
             let data = simulator.get_input_value(&self.write_data);
             trace!("write data {:?}", data);
@@ -177,6 +177,7 @@ impl Component for RegFile {
         let reg_value_b = self.read_reg(simulator, &self.read_addr2);
         trace!("reg_value_b {:?}", reg_value_b);
         simulator.set_out_value(&self.id, "reg_b", reg_value_b);
+        Ok(())
     }
 }
 

riscv/src/components/sign_zero_ext.rs

@@ -1,6 +1,6 @@
 use log::trace;
 use serde::{Deserialize, Serialize};
-use syncrim::common::{Component, Input, OutputType, Ports, SignalValue, Simulator};
+use syncrim::common::{Component, Condition, Input, OutputType, Ports, SignalValue, Simulator};
 
 #[derive(Serialize, Deserialize)]
 pub struct SZExt {
@@ -27,13 +27,12 @@ impl Component for SZExt {
         )
     }
     #[allow(non_snake_case)]
-    fn clock(&self, simulator: &mut Simulator) {
+    fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> {
         //data is zero extended as default since its a 32 bit signal
 
         match simulator.get_input_value(&self.data_i) {
             //if there is data, sel should be defined, otherwise panic is good.
-            SignalValue::Data(data) => {
-                let mut data: u32 = data.try_into().unwrap();
+            SignalValue::Data(mut data) => {
                 let sel: u32 = simulator.get_input_value(&self.sel_i).try_into().unwrap();
                 //println!("SZEDATA:{:x}", data);
                 match sel {
@@ -56,6 +55,7 @@ impl Component for SZExt {
             }
             _ => simulator.set_out_value(&self.id, "out", SignalValue::Unknown),
         }
+        Ok(())
     }
 }
 

src/common.rs

@@ -62,12 +62,22 @@ pub trait Component {
     fn get_id_ports(&self) -> (Id, Ports);
 
     /// evaluate component based on current internal state
-    fn clock(&self, _simulator: &mut Simulator) {}
+    fn clock(&self, _simulator: &mut Simulator) -> Result<(), Condition> {
+        Ok(())
+    }
 
     /// update component internal state
     fn un_clock(&self) {}
 }
 
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub enum Condition {
+    Warning(String),
+    Error(String),
+    Assert(String),
+    Halt(String),
+}
+
 // Specific functionality for EGui frontend
 #[cfg(feature = "gui-egui")]
 #[typetag::serde(tag = "type")]