changelog

perlindgren · Jul 25, 2023 · ac16cb1 · ac16cb1
1 parent 3292501
commit ac16cb1
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,6 +4,8 @@ Tracking changes per date:
 
 ## 230725
 
+- Added RISC-V components and model
+
 - Implemented the `ProbeAssert` component, that assert a set sequence of inputs. Made some updates so reading outside of the assert/stim buffers gives `Signal::Unknown` instead of panic (if not in test mode).
 
   Asserts are run only in test mode, allowing gui testing to be more robust.