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perlindgren · Jul 31, 2023 · d4bf2d2 · d4bf2d2
1 parent 5d99017
commit d4bf2d2
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Showing 5 changed files with 9 additions and 7 deletions.
diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -30,6 +30,7 @@
     "repr",
     "rgbaf",
     "rgbf",
+    "riscv",
     "rustfmt",
     "serde",
     "stim",
@@ -47,12 +48,12 @@
   "[rust]": {
     "editor.defaultFormatter": "rust-lang.rust-analyzer",
     "editor.formatOnSave": true
-  },
+  }
   //,
   // "rust-analyzer.cargo.unsetTest": [
   //   "syncrim"
   // ],
   // "rust-analyzer.cargo.noDefaultFeatures": true,
   // "rust-analyzer.cargo.features": ["gui-egui"]
   // "rust-analyzer.cargo.features": ["components"] # use with nDefaultFeatures to just test
-}
+}
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -2,6 +2,10 @@
 
 Tracking changes per date:
 
+## 230731
+
+- RISC-V cross compilation.
+
 ## 230727
 
 - `Signal` type now incorporates formatting. This allows the default formatting to be set on a signal on creation. The data and formatting can be read/written separately by setters/getters.

diff --git a/riscv/asm.s b/riscv/asm.s
@@ -3,6 +3,7 @@
 start:
     lw x0, 0(x0)
     sw x1, 0(x1)
+l:  beq zero, zero, l
 
 .section .data 
 a:  .byte 0,1,2,3

diff --git a/riscv/riscv_asm/build.rs b/riscv/riscv_asm/build.rs
diff --git a/src/components/mem.rs b/src/components/mem.rs
@@ -87,6 +87,7 @@ impl Mem {
         ))
     }
 
+    #[allow(clippy::too_many_arguments)]
     pub fn rc_new_from_bytes(
         id: &str,
         pos: (f32, f32),