Merge pull request #41 from perlindgren/probe_stim

Probe stim

.vscode/settings.json

@@ -30,6 +30,7 @@
     "rgbf",
     "rustfmt",
     "serde",
+    "stim",
     "struct",
     "stylesheet",
     "syncrim",

CHANGELOG.md

@@ -2,6 +2,12 @@
 
 Tracking changes per date:
 
+## 230725
+
+- Refactored, `clock` as `cycle` and put it in the `Simulator` (thanks to Fredrik for suggesting this a while back). Now the Simulator holds the complete state, which is better.
+
+- Implemented the `ProbeStim` component, to provide a set sequence of outputs.
+
 ## 230721
 
 - Added rudimentary support for a structured `Signal` type, inspired by HDLs.

mips/src/components/reg_file.rs

@@ -215,10 +215,10 @@ mod test {
                 }),
             ],
         };
-        let mut clock = 0;
-        let mut simulator = Simulator::new(&cs, &mut clock);
 
-        assert_eq!(clock, 1);
+        let mut simulator = Simulator::new(&cs);
+
+        assert_eq!(simulator.cycle, 1);
 
         // outputs
         let out_reg_1 = &Input::new("reg_file", "reg_a");
@@ -238,9 +238,9 @@ mod test {
         // test write and read to reg # 1 in same cycle
         println!("sim_state {:?}", simulator.sim_state);
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
         println!("sim_state {:?}", simulator.sim_state);
-        assert_eq!(clock, 2);
+        assert_eq!(simulator.cycle, 2);
         assert_eq!(simulator.get_input_val(out_reg_1), 0.into());
         assert_eq!(simulator.get_input_val(out_reg_2), 1337.into());
 
@@ -252,9 +252,9 @@ mod test {
         simulator.set_out_val("write_addr", "out", 0);
         simulator.set_out_val("write_enable", "out", true as SignalUnsigned);
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
         println!("sim_state {:?}", simulator.sim_state);
-        assert_eq!(clock, 3);
+        assert_eq!(simulator.cycle, 3);
         assert_eq!(simulator.get_input_val(out_reg_1), 0.into());
         assert_eq!(simulator.get_input_val(out_reg_2), 1337.into());
     }

src/common.rs

@@ -59,6 +59,7 @@ type Components = Vec<Rc<dyn EguiComponent>>;
 #[cfg_attr(feature = "gui-vizia", derive(Lens))]
 #[derive(Clone)]
 pub struct Simulator {
+    pub cycle: usize,
     pub id_start_index: IdStartIndex,
 
     // Components stored in topological evaluation order

src/components/add.rs

@@ -85,10 +85,9 @@ mod test {
                 }),
             ],
         };
-        let mut clock = 0;
-        let mut simulator = Simulator::new(&cs, &mut clock);
+        let mut simulator = Simulator::new(&cs);
 
-        assert_eq!(clock, 1);
+        assert_eq!(simulator.cycle, 1);
 
         // outputs
         let add_val = &Input::new("add", "out");
@@ -106,9 +105,10 @@ mod test {
         simulator.set_out_val("po2", "out", 1337);
         println!("sim_state {:?}", simulator.sim_state);
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
+
         println!("sim_state {:?}", simulator.sim_state);
-        assert_eq!(clock, 2);
+        assert_eq!(simulator.cycle, 2);
         assert_eq!(simulator.get_input_val(add_val), (42 + 1337).into());
         assert_eq!(
             simulator.get_input_val(add_overflow),
@@ -121,9 +121,9 @@ mod test {
         simulator.set_out_val("po2", "out", 1);
         println!("sim_state {:?}", simulator.sim_state);
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
         println!("sim_state {:?}", simulator.sim_state);
-        assert_eq!(clock, 3);
+        assert_eq!(simulator.cycle, 3);
         assert_eq!(
             simulator.get_input_val(add_val),
             (SignalUnsigned::MAX / 2 + 1).into()

src/components/mem.rs

@@ -274,10 +274,9 @@ mod test {
             ],
         };
 
-        let mut clock = 0;
-        let mut simulator = Simulator::new(&cs, &mut clock);
+        let mut simulator = Simulator::new(&cs);
 
-        assert_eq!(clock, 1);
+        assert_eq!(simulator.cycle, 1);
 
         // outputs
         let out = &Input::new("mem", "data");
@@ -299,10 +298,10 @@ mod test {
         println!("sim_state {:?}", simulator.sim_state);
 
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
         println!("sim_state {:?}", simulator.sim_state);
 
-        assert_eq!(clock, 2);
+        assert_eq!(simulator.cycle, 2);
         assert_eq!(simulator.get_input_val(out), 0.into());
         assert_eq!(
             simulator.get_input_val(err),
@@ -314,9 +313,9 @@ mod test {
         simulator.set_out_val("ctrl", "out", MemCtrl::Read as SignalUnsigned);
         simulator.set_out_val("size", "out", 1);
 
-        simulator.clock(&mut clock);
+        simulator.clock();
 
-        assert_eq!(clock, 3);
+        assert_eq!(simulator.cycle, 3);
         assert_eq!(simulator.get_input_val(out), 0xf0.into());
         assert_eq!(
             simulator.get_input_val(err),
@@ -327,8 +326,8 @@ mod test {
         simulator.set_out_val("size", "out", 1);
         simulator.set_out_val("sign", "out", true);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 4);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 4);
         assert_eq!(simulator.get_input_val(out), 0xffff_fff0.into());
         assert_eq!(
             simulator.get_input_val(err),
@@ -339,8 +338,8 @@ mod test {
         simulator.set_out_val("size", "out", 2);
         simulator.set_out_val("sign", "out", true as SignalUnsigned);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 5);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 5);
         assert_eq!(simulator.get_input_val(out), 0xffff_f000.into());
         assert_eq!(
             simulator.get_input_val(err),
@@ -351,72 +350,72 @@ mod test {
         simulator.set_out_val("size", "out", 4);
         simulator.set_out_val("sign", "out", true);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 6);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 6);
         assert_eq!(simulator.get_input_val(out), 0xf000_0000.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read word from addr 5>");
         simulator.set_out_val("addr", "out", 5);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 7);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 7);
         assert_eq!(simulator.get_input_val(err), true.into());
 
         println!("<setup for read word from addr 6>");
         simulator.set_out_val("addr", "out", 6);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 8);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 8);
         assert_eq!(simulator.get_input_val(err), true.into());
 
         println!("<setup for read word from addr 7>");
         simulator.set_out_val("addr", "out", 7);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 9);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 9);
         assert_eq!(simulator.get_input_val(err), true.into());
 
         println!("<setup for read word from addr 8>");
         simulator.set_out_val("addr", "out", 8);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 10);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 10);
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read half-word from addr 9>");
         simulator.set_out_val("addr", "out", 9);
         simulator.set_out_val("size", "out", 2);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 11);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 11);
         assert_eq!(simulator.get_input_val(err), true.into());
 
         println!("<setup for read half-word from addr 10>");
         simulator.set_out_val("addr", "out", 10);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 12);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 12);
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for write half-word at add 10>");
         simulator.set_out_val("addr", "out", 10);
         simulator.set_out_val("data", "out", 0x1234);
         simulator.set_out_val("ctrl", "out", MemCtrl::Write as SignalUnsigned);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 13);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 13);
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read byte at add 10>");
         simulator.set_out_val("ctrl", "out", MemCtrl::Read as SignalUnsigned);
         simulator.set_out_val("size", "out", 1);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 14);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 14);
         assert_eq!(simulator.get_input_val(out), 0x12.into());
 
         println!("<setup for read byte at add 11>");
         simulator.set_out_val("addr", "out", 11);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 15);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 15);
         assert_eq!(simulator.get_input_val(out), 0x34.into());
 
         println!("test done")
@@ -456,10 +455,9 @@ mod test {
             ],
         };
 
-        let mut clock = 0;
-        let mut simulator = Simulator::new(&cs, &mut clock);
+        let mut simulator = Simulator::new(&cs);
 
-        assert_eq!(clock, 1);
+        assert_eq!(simulator.cycle, 1);
 
         // outputs
         let out = &Input::new("mem", "data");
@@ -479,10 +477,10 @@ mod test {
         println!("sim_state {:?}", simulator.sim_state);
 
         println!("<clock>");
-        simulator.clock(&mut clock);
+        simulator.clock();
         println!("sim_state {:?}", simulator.sim_state);
 
-        assert_eq!(clock, 2);
+        assert_eq!(simulator.cycle, 2);
         assert_eq!(simulator.get_input_val(out), 0.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
@@ -491,35 +489,35 @@ mod test {
         simulator.set_out_val("ctrl", "out", MemCtrl::Read as SignalUnsigned);
         simulator.set_out_val("size", "out", 1);
 
-        simulator.clock(&mut clock);
+        simulator.clock();
 
-        assert_eq!(clock, 3);
+        assert_eq!(simulator.cycle, 3);
         assert_eq!(simulator.get_input_val(out), 0xf0.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read byte from addr 4>");
         simulator.set_out_val("size", "out", 1);
         simulator.set_out_val("sign", "out", true);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 4);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 4);
         assert_eq!(simulator.get_input_val(out), 0xffff_fff0.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read half-word from addr 4>");
         simulator.set_out_val("size", "out", 2);
         simulator.set_out_val("sign", "out", true);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 5);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 5);
         assert_eq!(simulator.get_input_val(out), 0x0000_00f0.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read word from addr 4>");
         simulator.set_out_val("size", "out", 4);
         simulator.set_out_val("sign", "out", true);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 6);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 6);
         assert_eq!(simulator.get_input_val(out), 0x0000_00f0.into());
         assert_eq!(simulator.get_input_val(err), false.into());
 
@@ -529,21 +527,21 @@ mod test {
         simulator.set_out_val("ctrl", "out", MemCtrl::Write as SignalUnsigned);
         simulator.set_out_val("size", "out", 2);
 
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 7);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 7);
         assert_eq!(simulator.get_input_val(err), false.into());
 
         println!("<setup for read byte at add 10>");
         simulator.set_out_val("ctrl", "out", MemCtrl::Read as SignalUnsigned);
         simulator.set_out_val("size", "out", 1);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 8);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 8);
         assert_eq!(simulator.get_input_val(out), 0x34.into());
 
         println!("<setup for read byte at add 11>");
         simulator.set_out_val("addr", "out", 11);
-        simulator.clock(&mut clock);
-        assert_eq!(clock, 9);
+        simulator.clock();
+        assert_eq!(simulator.cycle, 9);
         assert_eq!(simulator.get_input_val(out), 0x12.into());
     }
 }

src/components/mod.rs

@@ -5,6 +5,7 @@ mod mux;
 mod probe;
 mod probe_edit;
 mod probe_out;
+mod probe_stim;
 mod register;
 mod sext;
 mod wire;
@@ -16,6 +17,7 @@ pub use mux::*;
 pub use probe::*;
 pub use probe_edit::*;
 pub use probe_out::*;
+pub use probe_stim::*;
 pub use register::*;
 pub use sext::*;
 pub use wire::*;

src/components/probe.rs

@@ -1,6 +1,7 @@
 use crate::common::{Component, Id, Input, OutputType, Ports};
 use log::*;
 use serde::{Deserialize, Serialize};
+use std::rc::Rc;
 #[derive(Serialize, Deserialize)]
 pub struct Probe {
     pub id: Id,
@@ -27,3 +28,17 @@ impl Component for Probe {
         )
     }
 }
+
+impl Probe {
+    pub fn new(id: &str, pos: (f32, f32), input: Input) -> Self {
+        Probe {
+            id: id.to_string(),
+            pos,
+            input,
+        }
+    }
+
+    pub fn rc_new(id: &str, pos: (f32, f32), input: Input) -> Rc<Self> {
+        Rc::new(Probe::new(id, pos, input))
+    }
+}