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Sequantial componets evalultion order fix #88

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merged 2 commits into from
Oct 3, 2024

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Spooky-Firefox
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This PR is to solve the problem that arises from evaluation order of sequential components by adding the constraint that there can't be any sequential to sequential connections

an example, let r_n be registers, a sequential component, and gc a group of combinatorial logic components. Suppose we have an network as described below

r_1 -> r_2 -> gc -> back to r1

where default for registers are 0, and for gc its 10

currently syncrim could order the evaluation as shown below (note that sequential always are evaluated first)

r1, r2, gc

when evaluating:

  1. r1 reads 10 from gc and sets r1_out = 10
  2. r2 reads 10 from r1 and sets r2_out = 10

In this example the value passed through 2 registers in one cycle which is not the intended behavior.

By adding the constraint that there should be no sequential to sequential connections we ensure that the evaluation of an sequential component can’t directly affect another sequential component. This leads to the order of sequential component evaluation doesn't matter.

A pass through component were also added to that can be used between sequential components

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@salon64 salon64 left a comment

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works!

@salon64 salon64 merged commit ff64ab2 into perlindgren:master Oct 3, 2024
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2 participants