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Langage-VHDL---Exemple-code-

Code Examples in VHDL devlopped on Quartus II dev platform

See also the follow pages : https://fixme.ch/wiki/Langage_VHDL & https://fixme.ch/wiki/Talk:Langage_VHDL

Project 1 - 7 SEGMENTS DISPLAY [DONE] :

With an electronics board created by the ETML-ES School and equiped with a FPGA, realization of logic schemtatics concerning the 7 Segments dispaly (0 to F) under Quartus.

Project 2 - JUNGLER [IN PROGRESS - PART A -> DONE]:

With an electronics board created by the ETML-ES School and equiped with a FPGA, realization / Simulation of a juggler with the both 7 Segments Display

Project 3 - JOYEUX NOEL [DONE] :

With an electronics board created by the ETML-ES School and equiped with a FPGA, realization / Simulation of a programme in VHDL which allows to read a message in a message implemented in the FPGA (in the code - constant table) and to display the message on the two 7 segments display. The message rolls out at the 500ms (Time).

Project 4 - Counter 0 to 9 [DONE] :

With an electronics board created by the ETML-ES School and equiped with a FPGA(EMP1270T144C5), realization program in VHDL which allows to display on 7SEG screen the values of 0 to 9 (counter). Two switches will allow to select 4 different frequencies (1Hz, 2Hz, 500Hz, 1kHz) and two others will allow to configure the functional mode (START/STOP + increment/decrement counter)

Project 5 - Effect mirror on the 7 Seg displays [DONE] :

With an electronics board created by the ETML-ES School and equiped with a FPGA(EMP1270T144C5), realization program in VHDL which allows to display on 7SEG screen the values of A to D, the first degment displays normaly the value, and on the second display allows to see the letter inverted either horizontal or vertical. Two switches will allow to select 4 different mode : NORMAL - HORIZONTAL - VERTCIAL - NO DISPLAY.

Project 6 - CADENAS V0.3 [DONE] :

With an electronics board created by the ETML-ES School and equiped with a FPGA(EMP1270T144C5), realization program in VHDL which allows to simulate the behavior of a padlock. 2 switches are used to 3 modes : rest / recording the new code / reading. 4 switches allow to record a new code or to read the code

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Code Examples in VHDL devlopped on Quartus II dev platform

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