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boards: icicle: update linker scripts to use the 2023.02 memory map
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Update the master and remote linker scripts for the mpfs-rpmsg-bm
and mpfs-rpmsg-freertos projects to use DDR 38-bit cached memory and
to match with the addresses defined in the 2023.02 release memory map.

Signed-off-by: Valentina Fernandez <[email protected]>
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@vfalanis
vfalanis committed Jan 31, 2023
1 parent c894029 commit f592c6b
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Showing 4 changed files with 16 additions and 16 deletions.
8 changes: 4 additions & 4 deletions .../src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-master.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,9 @@ MEMORY
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 4M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 128M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 128M
ddr_cached_32bit (rwx) : ORIGIN = 0x91800000, LENGTH = 1M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
Expand Down Expand Up @@ -106,7 +106,7 @@ STACK_SIZE_U54_4_APPLICATION = 8k;


/* reset address 0xC0000000 */
SECTION_START_ADDRESS = 0x80000000;
SECTION_START_ADDRESS = 0x91800000;


SECTIONS
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8 changes: 4 additions & 4 deletions .../src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-remote.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,9 @@ MEMORY
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x81000000, LENGTH = 4M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 128M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 128M
ddr_cached_32bit (rwx) : ORIGIN = 0x91C00000, LENGTH = 1M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
Expand Down Expand Up @@ -106,7 +106,7 @@ STACK_SIZE_U54_4_APPLICATION = 8k;


/* reset address 0xC0000000 */
SECTION_START_ADDRESS = 0x81000000;
SECTION_START_ADDRESS = 0x91C00000;


SECTIONS
Expand Down
8 changes: 4 additions & 4 deletions .../src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-master.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,9 @@ MEMORY
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 4M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 128M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 128M
ddr_cached_32bit (rwx) : ORIGIN = 0x91800000, LENGTH = 1M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
Expand Down Expand Up @@ -106,7 +106,7 @@ STACK_SIZE_U54_4_APPLICATION = 8k;


/* reset address 0xC0000000 */
SECTION_START_ADDRESS = 0x80000000;
SECTION_START_ADDRESS = 0x91800000;


SECTIONS
Expand Down
8 changes: 4 additions & 4 deletions .../src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-remote.ld
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,9 @@ MEMORY
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x81000000, LENGTH = 4M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 128M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 128M
ddr_cached_32bit (rwx) : ORIGIN = 0x91C00000, LENGTH = 1M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
Expand Down Expand Up @@ -106,7 +106,7 @@ STACK_SIZE_U54_4_APPLICATION = 8k;


/* reset address 0xC0000000 */
SECTION_START_ADDRESS = 0x81000000;
SECTION_START_ADDRESS = 0x91C00000;


SECTIONS
Expand Down

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