Export from devel repo

48MHz version for STM32F102CB and 96MHz for MH2103A CB

	modified:   src/Makefile.STM32F102
	modified:   src/Makefile.console
	modified:   src/card_os/debug.h
	modified:   src/lib/ARM/bn_lib_arm_cm3.c
	modified:   src/targets/STM32F102/LED.h
	modified:   src/targets/STM32F102/STM32F10x_dev_init.c
	modified:   src/targets/STM32F102/serial_debug.c

src/Makefile.STM32F102

@@ -3,14 +3,24 @@
 #
 # Please, check if your STLINKv2 is based on STM32F102/STM32F103 MCU or
 # MH2103 MCU. Depends on it use:
-# make -f Makefile.STM32F102 programST
+# make -f Makefile.STM32F102 programSTM
 # make -f Makefile.STM32F102 programMH
 #
 # For FLASH erase:
-# make -f Makefile.STM32F102 unlockST
+# make -f Makefile.STM32F102 unlockSTM
 # make -f Makefile.STM32F102 unlockMH
 # (You may have to ground the reset pin (by shorting pin 7 and 8)
 #
+
+# Default is STM32F103CB, but if your MCU is STM32F102CB, you may have a
+# problem with the fact that it runs at 72MHz, but the manufacturer allows
+# only 48MHz. In that case below enable STM32F102CB and block STM32F103CB
+# (there is no difference between the MH2103ACB and STM32F103CB versions)
+
+#MCU_IDENT = __STM32F102CB__
+MCU_IDENT = __STM32F103CB__
+#MCU_IDENT = __MH2103ACB__
+
 ARMGNU = arm-none-eabi
 MCU_SPEC  = cortex-m3
 
@@ -29,6 +39,7 @@ ASFLAGS += -Wall
 ASFLAGS += -fmessage-length=0
 
 CFLAGS += -mcpu=$(MCU_SPEC)
+CFLAGS += -D$(MCU_IDENT)
 CFLAGS += -mthumb
 CFLAGS += -Wall
 CFLAGS += -g
@@ -178,16 +189,16 @@ $(BUILD)/card.bin:	$(BUILD)/card.elf
 	$(OC) -S -O binary $(BUILD)/card.elf $(BUILD)/card.bin
 
 
-programST:	$(BUILD)/card.bin
+programSTM:	$(BUILD)/card.bin
 	openocd -f interface/stlink.cfg -f target/stm32f1x.cfg -c init -c "reset halt" -c "flash write_image erase $(BUILD)/card.bin 0x08000000 bin" -c "reset" -c "shutdown"
 
-readST:
+readSTM:
 	openocd -f interface/stlink.cfg -f target/stm32f1x.cfg -c init -c "reset halt" -c "flash read_bank 0 STM32F102CB_flash_read.bin 0 131072"  -c "reset" -c "shutdown"
 
-unlockST:
+unlockSTM:
 	openocd -f interface/stlink.cfg -f target/stm32f1x.cfg -c init -c "reset halt" -c "stm32f1x unlock 0" -c "reset halt" -c "stm32f1x mass_erase 0" -c "reset" -c "shutdown"
 
-readoptionsST:
+readoptionsSTM:
 	openocd -f interface/stlink.cfg -f target/stm32f1x.cfg -c init -c "reset halt" -c "stm32f1x options_read 0" -c "reset" -c "shutdown"
 
 programMH:	$(BUILD)/card.bin

src/Makefile.console

@@ -16,6 +16,8 @@ CFLAGS+= -DRSA_BYTES=128 -DCARD_RESTART -I$(TARGET)
 # to test prime generator:
 #grep 0x rsa_gen_debug.stat|awk '{print "IsPrime("$1")"}' |genius|grep -v true
 
+CFLAGS += -DDEBUG_DEVEL
+
 CC= gcc
 ##CFLAGS+= -D_FORTIFY_SOURCE=2
 #CC= cgcc -Wsparse-all

src/card_os/debug.h

@@ -73,7 +73,7 @@
 #endif
 
 
-#if !(defined __arm__) && !(defined __AVR__) && defined (DEBUG_V)
+#if defined(DEBUG_DEVEL) && defined (DEBUG_V)
 #include <stdlib.h>
 #include <stdio.h>
 #define DPRINT(msg...) {char *env_atr = getenv ("OsEID_DEBUG"); if(env_atr){if(atoi(env_atr)& DEBUG_V){fprintf(stderr,msg);}}}

src/lib/ARM/bn_lib_arm_cm3.c

@@ -568,7 +568,7 @@ static void
 #pragma GCC diagnostic pop
 // only low part of multiplication is needed (64 bytes..)
 // len is 64 maximum (for RSA 2048) ..
-void bn_mul_mod_v(uint8_t * R, uint8_t * A, uint8_t * B, uint8_t len)
+void __attribute__((aligned(8))) bn_mul_mod_v(uint8_t * R, uint8_t * A, uint8_t * B, uint8_t len)
 {
 	uint32_t *r32 = (uint32_t *) R;
 	uint32_t *a32 = (uint32_t *) A;
@@ -582,7 +582,7 @@ void bn_mul_mod_v(uint8_t * R, uint8_t * A, uint8_t * B, uint8_t len)
 }
 
 #if 1
-void bn_mul_v(void *R, void *A, void *B, uint8_t len)
+void __attribute__((aligned(8))) bn_mul_v(void *R, void *A, void *B, uint8_t len)
 {
 	uint32_t *r = (uint32_t *) R;
 	uint32_t *a = (uint32_t *) A;
@@ -678,7 +678,7 @@ void __attribute__((naked)) bn_mul_v(void *R, void *A, void *B, uint8_t len)
 }
 #endif
 #if 1
-uint32_t bn_mul_add_v(void *R, void *A, void *B, uint8_t len)
+uint32_t __attribute__((aligned(8))) bn_mul_add_v(void *R, void *A, void *B, uint8_t len)
 {
 	uint32_t *r = (uint32_t *) R;
 	uint32_t *a = (uint32_t *) A;

src/targets/STM32F102/LED.h

@@ -28,6 +28,12 @@
 // RUN  = command parsing/response generating
 
 #ifndef SERIAL_DEBUG
+void led1_on(void);
+void led1_off(void);
+void led1_toggle(void);
+void led2_on(void);
+void led2_off(void);
+
 // led is on on idle, of on run
 #define LED1_INIT()
 #define LED1_BUSY()	led1_toggle()

src/targets/STM32F102/STM32F10x_dev_init.c

@@ -56,6 +56,139 @@ static void enable_GPIOA_clock()
 	address[0x18 / 4] |= 4;
 }
 
+#ifdef __STM32F102CB__
+static void __attribute__((unused)) RCC_setup()
+{
+/*
+	PLL is running on 48MHz (from HSE xtal 8MHz)
+	1 is division factor for USB (48MHz)
+
+	APB1 max = 24MHz
+	APB2 max = 48MHz
+	AHB max - 48MHz
+	ADC max is 14MHz, from APB2 ->divisor 4, -> 12MHz
+*/
+
+	volatile uint32_t *address = (uint32_t *) (RCC_BASE);
+
+	// enable XTAL oscillator (8MHz)
+	address[0] |= (1 << 16);	//RCC_RC |= HSEON
+	// wait for HSE stable
+	while (!(address[0] & (1 << 17))) ;	// RCC_RC, HSERDY
+
+	// PLL source HSE (PLLSRC)
+	address[1] = (1 << 16);
+	// set pll factor (6x8=48MHz)
+	address[1] |= (4 << 18);
+	// enable PLL
+	address[0] |= (1 << 24);	//RCC_RC |= PLL_ON
+	// wait for PLL stable
+	while (!(address[0] & (1 << 25))) ;
+
+	// APB1 prescaler = 2
+	address[1] |= (4 << 8);
+
+	// ADC clock - 48MHz / 4 -> 12MHz
+	address[1] |= (1 << 14);
+
+	// for 24..48MHz two wait states for flash
+	address = (uint32_t *) (FLASH_R_BASE);
+	address[0] |= 1;	// FLASH_ACR register, bit 2,1,0 = latency
+
+	// switch system to PLL clock
+	address = (uint32_t *) (RCC_BASE);
+	address[1] |= 2;
+
+	// usb clock divisor = 1
+	address[1] |= (1 << 22);
+
+	// wait for system clock switch to PLL
+	while ((address[1] & 0x0c) != 8) ;
+
+	// enable TIM2 clock
+	address[0x1c / 4] |= (1 << 0);
+
+	// enable USB clock
+	address[0x1c / 4] |= (1 << 23);
+
+	// reset USB clock
+//      address[0x10 / 4] |= (1 << 23);
+//      address[0x10 / 4] &= ~(1 << 23);
+
+	// enable ADC1 clock (ADC is used for random generator)
+	address[0x18 / 4] = (1 << 9);
+
+}
+#elif defined(__MH2103ACB__)
+static void RCC_setup()
+{
+/*
+	APB1 max = 108MHz
+	APB2 max = 216MHz
+	AHB max = 216HHz
+	ADC max = 14MHz, from APB2
+	// 108..216 1 wait state
+
+	PLL is running on 96MHz (from HSE xtal 8MHz)
+	2 is division factor for USB (48MHz)
+
+	APB1 max = 48MHz
+	APB2 max = 96MHz
+	AHB max - 96HHz
+	ADC max is 14MHz, from APB2 ->divisor 8, -> 12MHz
+*/
+
+	volatile uint32_t *address = (uint32_t *) (RCC_BASE);
+
+	// enable XTAL oscillator (8MHz)
+	address[0] |= (1 << 16);	//RCC_RC |= HSEON
+	// wait for HSE stable
+	while (!(address[0] & (1 << 17))) ;	// RCC_RC, HSERDY
+
+	// PLL source HSE (PLLSRC)
+	address[1] = (1 << 16);
+	// set pll factor (12x8=96MHz)
+	address[1] |= 0x00280000;	// 96MHz
+	// USB 96MHz /2
+	address[1] |= 0x00C00000;
+
+	// enable PLL
+	address[0] |= (1 << 24);	//RCC_RC |= PLL_ON
+	// wait for PLL stable
+	while (!(address[0] & (1 << 25))) ;
+
+	// APB1 prescaler = 2
+	address[1] |= (4 << 8);
+
+	// ADC clock - 96MHz / 8 -> 12MHz
+	address[1] |= 0x0000C000;
+
+	// for 108.. 216 z two wait states for flash
+	address = (uint32_t *) (FLASH_R_BASE);
+	address[0] |= 1;	// FLASH_ACR
+
+	// switch system to PLL clock
+	address = (uint32_t *) (RCC_BASE);
+	address[1] |= 2;
+
+	// wait for system clock switch to PLL
+	while ((address[1] & 0x0c) != 8) ;
+
+	// enable TIM2 clock
+	address[0x1c / 4] |= (1 << 0);
+
+	// enable USB clock
+	address[0x1c / 4] |= (1 << 23);
+
+	// reset USB clock
+//      address[0x10 / 4] |= (1 << 23);
+//      address[0x10 / 4] &= ~(1 << 23);
+
+	// enable ADC1 clock (ADC is used for random generator)
+	address[0x18 / 4] = (1 << 9);
+
+}
+#else
 static void RCC_setup()
 {
 /*
@@ -115,7 +248,7 @@ static void RCC_setup()
 	address[0x18 / 4] = (1 << 9);
 
 }
-
+#endif
 //// USB
 #define EP0R (0/4)
 #define EP1R (4/4)
@@ -814,30 +947,28 @@ void get_HW_serial_number(uint8_t here[10])
 	}
 }
 
+static void nostart()
+{
+// stop her if PB12 /SWDIO/ is grouned
+	// GPIOB...
+	volatile uint32_t *address;
+	address = (uint32_t *) (RCC_BASE);
+	address[0x18 / 4] |= 8;
+	address = (uint32_t *) GPIOB_BASE;
+	address[1] = 0x48484444;
+	// activate pull-up
+	address[0x10 / 4] = (1 << 12) | (1 << 14);
+	// read state
+	while (!(address[0x8 / 4] & (1 << 12))) ;
+}
+
 void init_stm()
 {
 	RCC_setup();
 	enable_GPIOA_clock();
 	init_GPIOA_pins();
 	DEBUG_init();
-#ifdef SERIAL_DEBUG
-	{
-// stop if PA12 is grouned (to prevent suspend and
-// allow flash the device without RESET)
-		// GPIOB...
-		volatile uint32_t *address;
-		address = (uint32_t *) (RCC_BASE);
-		address[0x18 / 4] |= 8;
-		address = (uint32_t *) GPIOB_BASE;
-		address[1] = 0x48484444;
-		// activate pull-up
-		address[0x10 / 4] = (1 << 12) | (1 << 14);
-		// read state
-		DEBUG_print_hex16(address[0x8 / 4]);
-		while (!(address[0x8 / 4] & (1 << 12))) ;
-		DEBUG_print_string("P\n");
-	}
-#endif
+	nostart();
 	CCID_Init();
 	usbInit();
 	DEBUG_print_string("Init OK, starting main\n");

src/targets/STM32F102/serial_debug.c

@@ -45,9 +45,16 @@ void serial_init()
 // enable usart, enable TX
 	usart[3] = (1 << 13) | (1 << 3);	// CTRL1
 
+#if defined(__STM32F102CB__)
+// clock PCLK2 <- from APB2 prescaler[1] <- AHB prescaler [1] <- PLL [48 MHz]
+	usart[2] = 96;		// 500k
+#elif defined(__MH2103ACB__)
+// clock PCLK2 <- from APB2 prescaler[1] <- AHB prescaler [1] <- PLL [96 MHz]
+	usart[2] = 192;		// 500k
+#else
 // clock PCLK2 <- from APB2 prescaler[1] <- AHB prescaler [1] <- PLL [72 MHz]
 	usart[2] = 144;		// 500k
-
+#endif
 // overwrite GPIO pin function to alternate fcion - USART
 	gpio = (uint32_t *) GPIOA_BASE;
 	gpio[4 / 4] &= 0xFFFFFF0F;