Added option `--cpu' to support vexriscv{_smp}*

README.md

@@ -8,7 +8,7 @@ RISC-V processor is based on [VexRiscv][2] and implements the RV32IM
 architecture. Integration of peripherals such as external RAM, SD-card
 and USB is done though the [LiteX][3] framework.
 
-This fork supports `rv32imafds` instructions if `--with-fpu` is selected - see below.
+This fork supports `rv32imacfds` instructions if `--with-fpu --with-rvc` is selected - see below.
 Note that due to the FPGA limits, dual-core CPUs cannot be configured with FPU support.
 
 The bitstream includes an EXROM containing [BASIC extensions](doc/basic.md)
@@ -30,7 +30,7 @@ Warning: there's some heavy dependencies to your build-environment, especially w
 Example for building a single core CPU featuring FPU support with 80MHz frequency, with the console via USB:
 ```sh
 $ cd hw
-$ python3 bitstream.py --platform=orangecart --uart=usb_acm --sys-clk-freq=80e6 --cpu-count=1 --with-fpu --with-wishbone-memory
+$ python3 bitstream.py --platform=orangecart --uart=usb_acm --sys-clk-freq=80e6 --cpu-count=1 --with-fpu --with-rvc --with-wishbone-memory
 ```
 TODO: --with-wishbone-memory seems mandatory, should be made as default.
 
@@ -47,6 +47,10 @@ script:
 Specifies the hardware platform to target.  This is a mandatory argument.
 Currently only the value `orangecart` is valid.
 
+> --cpu {vexriscv,vexriscv_smp}
+
+Specifies which CPU core to choose. `vexriscv` is the *original* one, lightweigt. `vexriscv_smp` features more options, including several Riscv ISAs: ISA F/D/C in addition and SMP support. Checkout all options using `--help`.
+
 > --sys-clk-freq _SYS_CLK_FREQ_
 
 Changes the clock frequency of the RISC-V processor from the default of

hw/bitstream.py

@@ -12,6 +12,7 @@
 import contextlib
 import json
 import os
+import sys
 
 from litex.soc.integration.builder import Builder
 from litex.tools.litex_json2dts_zephyr import generate_dts_config, print_or_save
@@ -27,6 +28,10 @@ def main():
         "--platform", choices=["orangecart"], required=True,
         help="build for a particular hardware"
     )
+    cpu = parser.add_argument(
+        "--cpu", default="vexriscv", choices=["vexriscv", "vexriscv_smp"], 
+        help="Choose one of the supported VexRiscV CPUs"
+    )
     parser.add_argument(
         "--sys-clk-freq", default=64e6,
         help="System clock frequency (default=64MHz)"
@@ -51,13 +56,15 @@ def main():
     parser.add_argument(
         "--seed", type=int, default=1, help="seed to use in nextpnr"
     )
-    VexRiscvSMP.args_fill(parser)
     args, _ = parser.parse_known_args()
 
     # Select platform based arguments
     if args.platform == "orangecart":
         from rtl.platform.orangecart import Platform, add_platform_args, platform_argdict
 
+    if args.cpu == "vexriscv_smp":
+        VexRiscvSMP.args_fill(parser)
+
     # Add any platform dependent args
     add_platform_args(parser)
     args = parser.parse_args()
@@ -76,18 +83,27 @@ def main():
     output_dir = 'build'
     sw_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), "../sw"))
 
-    cpu_type = "vexriscv_smp"
-    #cpu_variant = "standard+debug"
-    cpu_variant = "linux"
-    VexRiscvSMP.args_read(args)
+    if args.cpu == "vexriscv_smp":
+        cpu_type = "vexriscv_smp"
+        cpu_variant = "linux"
+        VexRiscvSMP.args_read(args)
+    else:
+        cpu_type = "vexriscv"
+        cpu_variant = "standard+debug"
+    if not os.path.exists(output_dir):
+        os.mkdir(output_dir)
+    f = open(os.path.join(output_dir, "build-commandline.log"), "w")
+    for arg in enumerate(sys.argv):
+        f.write(str(arg[1]) + " ")
+    f.write("\n")
+    f.close()
 
     soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant,
                   uart_name="stream" if args.uart is None else args.uart,
                   usb=args.usb, with_jtagbone=args.jtag_debug,
                   with_uartbone=args.serial_debug,
                   uartbone_baudrate=args.serial_debug_baudrate,
                   clk_freq=int(float(args.sys_clk_freq)),
-                  with_fpu=True,
                   output_dir=output_dir)
     builder = Builder(soc, output_dir=output_dir,
                       csr_csv=os.path.join(output_dir, "csr.csv"),

hw/rtl/basesoc.py

@@ -32,6 +32,8 @@ def __init__(self):
 
 class BaseSoC(SoCCore):
 
+    # these maps are vexriscv_smp as defined here, corrected for 
+    # vexriscv later in the constructor
     csr_map = {
         "ctrl":           0,
         "crg":            1,
@@ -69,13 +71,26 @@ def __init__(self, platform,
 
         self.output_dir = output_dir
 
+        # complement maps, in vexriscv_smp this is done by the cpu core
+        if kwargs['cpu_type'] == "vexriscv":
+            self.interrupt_map["uart"] = 0
+            self.interrupt_map["timer0"] = 1
+            self.csr_map["uart"] = 2
+            self.csr_map["timer0"] = 3
+            SoCCore.mem_map = {
+                "c64":              0x00000000,
+                "sram":             0x10000000,
+                "main_ram":         0x40000000,
+                "bios_rom":         0x70000000,
+                "csr":              0xf0000000,
+                "vexriscv_debug":   0xf00f0000,
+            }
+
         platform.add_crg(self, clk_freq,
                          uart_name=='usb_acm' or usb is not None)
 
         get_integrated_sram_size=getattr(platform, "get_integrated_sram_size",
                                          lambda: 0)
-        for i in kwargs:
-            print("[", i, "]=", kwargs[i], ",")
 
         SoCCore.__init__(self, platform, clk_freq, uart_name=uart_name,
                          cpu_reset_address=self.mem_map["bios_rom"],