Specification: PHY Interfaces

This specification documents possible PHY interfaces for Bitcoin FPGA Miners. See Components, Interfaces, and Protocols for information on all of the hardware protocols and interfaces. The last Component in the chain is a PHY; this document provides several possible interface specifications for that PHY.

The ultimate goal of any PHY interface to a Bitcoin FPGA Miner is to allow a Controller to talk to the Comm. The Comm is a memory mapped module, so the PHY must allow reading registers, and writing to registers (but not always writing, as there are Action-on-Write registers). The PHY interface should have error tolerance/correction built in.

The PHY should allow communication with multiple Comms, usually different FPGA or ASIC devices.

Expected Bandwidth: 1Kbit/s per Comm, +PHY Overhead.

##UART## TODO

##SPI## TODO

##JTAG## TODO