Merge pull request google#55 from mabrains/mos_iv_regression

Mos iv regression

models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nmos_3p3_cv.spice → models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_03v3.spice

@@ -34,7 +34,7 @@ vbs S_tn 0 dc=0
 * pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
 
 * circuit
-mn D_tn G_tn S_tn S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+mn 0 G_tn 0 S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
 
 .control
 set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
 
 	print @mn[cgb]
 
-        wrdata nfet_03v3_cv/simulated_Cgc/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
+        wrdata mos_cv_regr/nfet_03v3/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
 
         reset
         let vbs_counter = vbs_counter + 1

models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_06v0.spice

@@ -0,0 +1,74 @@
+***************************
+** nfet_06v0
+***************************
+* Copyright 2022 Efabless Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+** library calling
+
+.include "../../../design.ngspice"
+.lib "../../../sm141064.ngspice" typical
+
+
+** Circuit Description **
+* power supply
+vds D_tn 0 dc=0
+vgs G_tn 0 dc=6
+vbs S_tn 0 dc=0
+
+.temp 25
+.options tnom=25
+
+*l_diff_min = 0.24
+* ad = int((nf+1)/2) * width/nf * 0.24       = 24u                         
+* pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
+
+* circuit
+mn 0 G_tn 0 S_tn nfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+
+.control
+set filetype=ascii
+
+let vgs_min  = -6
+let vgs_step = 0.1
+let vgs_max  = 6
+
+compose  vbs_vector   start=0          stop=-3          step=-1
+
+set appendwrite
+
+foreach t 25
+
+    let vbs_counter = 0
+    while vbs_counter < length(vbs_vector)
+        option TEMP=25
+        alter vbs = vbs_vector[vbs_counter]
+
+        save  @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
+        *******************
+        ** simulation part
+        *******************
+        DC vgs $&vgs_min $&vgs_max $&vgs_step
+
+        * ** parameters calculation
+
+	print @mn[cgb]
+
+        wrdata mos_cv_regr/nfet_06v0/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
+
+        reset
+        let vbs_counter = vbs_counter + 1
+    end
+end
+.endc
+.end

models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/nfet_06v0_nvt.spice

@@ -0,0 +1,74 @@
+***************************
+** nfet_06v0
+***************************
+* Copyright 2022 Efabless Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+** library calling
+
+.include "../../../design.ngspice"
+.lib "../../../sm141064.ngspice" typical
+
+
+** Circuit Description **
+* power supply
+vds D_tn 0 dc=0
+vgs G_tn 0 dc=6
+vbs S_tn 0 dc=0
+
+.temp 25
+.options tnom=25
+
+*l_diff_min = 0.24
+* ad = int((nf+1)/2) * width/nf * 0.24       = 24u                         
+* pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
+
+* circuit
+mn 0 G_tn 0 S_tn nfet_06v0_nvt W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+
+.control
+set filetype=ascii
+
+let vgs_min  = -6
+let vgs_step = 0.1
+let vgs_max  = 6
+
+compose  vbs_vector   start=0          stop=-3          step=-1
+
+set appendwrite
+
+foreach t 25
+
+    let vbs_counter = 0
+    while vbs_counter < length(vbs_vector)
+        option TEMP=25
+        alter vbs = vbs_vector[vbs_counter]
+
+        save  @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
+        *******************
+        ** simulation part
+        *******************
+        DC vgs $&vgs_min $&vgs_max $&vgs_step
+
+        * ** parameters calculation
+
+	print @mn[cgb]
+
+        wrdata mos_cv_regr/nfet_06v0_nvt/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
+
+        reset
+        let vbs_counter = vbs_counter + 1
+    end
+end
+.endc
+.end

models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pmos_3p3_cv.spice → models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pfet_03v3.spice

@@ -34,7 +34,7 @@ vbs S_tn 0 dc=0
 * pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
 
 * circuit
-mn D_tn G_tn S_tn S_tn pfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+mn 0 G_tn 0 S_tn pfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
 
 .control
 set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
 
 	print @mn[cgb]
 
-        wrdata pfet_03v3_cv/simulated_Cgc/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
+        wrdata mos_cv_regr/pfet_03v3/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
 
         reset
         let vbs_counter = vbs_counter + 1

models/ngspice/testing/regression/mos_cv/device_netlists_Cgc/pfet_06v0.spice

@@ -0,0 +1,74 @@
+***************************
+** pfet_03v3_cv
+***************************
+* Copyright 2022 Efabless Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+** library calling
+
+.include "../../../design.ngspice"
+.lib "../../../sm141064.ngspice" typical
+
+
+** Circuit Description **
+* power supply
+vds D_tn 0 dc=0
+vgs G_tn 0 dc=6
+vbs S_tn 0 dc=0
+
+.temp 25
+.options tnom=25
+
+*l_diff_min = 0.24
+* ad = int((nf+1)/2) * width/nf * 0.24       = 24u                         
+* pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
+
+* circuit
+mn 0 G_tn 0 S_tn pfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+
+.control
+set filetype=ascii
+
+let vgs_min  = -6
+let vgs_step = 0.1
+let vgs_max  = 6
+
+compose  vbs_vector   start=0          stop=3.          step=1
+
+set appendwrite
+
+foreach t 25
+
+    let vbs_counter = 0
+    while vbs_counter < length(vbs_vector)
+        option TEMP=25
+        alter vbs = vbs_vector[vbs_counter]
+
+        save  @mn[vs] @mn[vgs] @mn[id] @mn[cgb]
+        *******************
+        ** simulation part
+        *******************
+        DC vgs $&vgs_min $&vgs_max $&vgs_step
+
+        * ** parameters calculation
+
+	print @mn[cgb]
+
+        wrdata mos_cv_regr/pfet_06v0/simulated_Cgc/simulated_W{{width}}_L{{length}}.csv {@mn[cgb]*1e15} 
+
+        reset
+        let vbs_counter = vbs_counter + 1
+    end
+end
+.endc
+.end

models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nmos_3p3_cv.spice → models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nfet_03v3.spice

@@ -24,7 +24,7 @@
 * power supply
 vds D_tn 0 dc=3.3
 vgs G_tn 0 dc=3.3
-vs S_tn 0 dc=0.2
+vs S_tn 0 dc=0
 
 .temp 25
 .options tnom=25
@@ -34,7 +34,7 @@ vs S_tn 0 dc=0.2
 * pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
 
 * circuit
-mn D_tn G_tn S_tn S_tn nfet_03v3 W = 200u L = 0.28u nf=20 ad= 24u pd=200.48u as=24u ps=200.48u
+mn D_tn G_tn S_tn S_tn nfet_03v3 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
 
 .control
 set filetype=ascii
@@ -64,7 +64,7 @@ foreach t 25
 
 	print @mn[cgd]
 
-        wrdata nfet_03v3_cv/simulated_Cgd/{{i}}_simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15} 
+        wrdata mos_cv_regr/nfet_03v3/simulated_Cgd/simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15} 
 
         reset
         let vgs_counter = vgs_counter + 1

models/ngspice/testing/regression/mos_cv/device_netlists_Cgd/nfet_06v0.spice

@@ -0,0 +1,74 @@
+***************************
+** nfet_03v3_cv
+***************************
+* Copyright 2022 Efabless Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+** library calling
+
+.include "../../../design.ngspice"
+.lib "../../../sm141064.ngspice" typical
+
+
+** Circuit Description **
+* power supply
+vds D_tn 0 dc=6
+vgs G_tn 0 dc=6
+vs S_tn 0 dc=0
+
+.temp 25
+.options tnom=25
+
+*l_diff_min = 0.24
+* ad = int((nf+1)/2) * width/nf * 0.24       = 24u                         
+* pd = (int((nf+1)/2) * width/nf + 0.24)*2   = 200.48u                 
+
+* circuit
+mn D_tn G_tn S_tn S_tn nfet_06v0 W = {{width}}u L = {{length}}u nf={{nf}} ad= 24u pd=200.48u as=24u ps=200.48u
+
+.control
+set filetype=ascii
+
+let vds_min  = 0
+let vds_step = 0.1
+let vds_max  = 6
+
+compose  vgs_vector   start=0          stop=6          step=2
+
+set appendwrite
+
+foreach t 25
+
+    let vgs_counter = 0
+    while vgs_counter < length(vgs_vector)
+        option TEMP=25
+        alter vgs = vgs_vector[vgs_counter]
+
+        save  @mn[vds] @mn[vgs] @mn[id] @mn[cgd]
+        *******************
+        ** simulation part
+        *******************
+        DC vds $&vds_min $&vds_max $&vds_step
+
+        * ** parameters calculation
+
+	print @mn[cgd]
+
+        wrdata mos_cv_regr/nfet_06v0/simulated_Cgd/simulated_W{{width}}_L{{length}}.csv {@mn[cgd]*1e15} 
+
+        reset
+        let vgs_counter = vgs_counter + 1
+    end
+end
+.endc
+.end